in verilog net names, which are apparently legal in verilog but not
in python strings (if not escaped). This is somewhat critical for
running the LVS GUI as yosys can generate backslashes in generated
net names in the synthesized netlist.
type double before sorting (previously, property promotion was
being done after parallel sorting). Also, modified the verilog
file reading so that parameters and definitions that are numeric
are stored as numeric (not string) properties.
perfect). Given the complexities of the verilog language, the simple
strtok() tokenizer used by the SPICE parser is not sufficient. Wrote
a better tokenizer that can distinguish between whitespace and
functional tokens like parentheses, semicolons, etc., which are tokens
themselves but also token separators.
determine if a parameter is a floating-point number, integer, or
string, and set the parameter accordingly. Found an error in the
parameter comparison if the subcircuit definitions don't agree
on the type of parameter. Now all values are promoted to a single
type based on preference order (double, integer, string). Tested
on a verilog file with a primitive device type defined as a module
with its properties encoded as parameters. This successfully
matched against the SPICE primitive device.
CDL syntax) parameters that have values which are multi-word and
space separated (who the hell comes up with these things?). One
can presumably safely assume that additional pin names are not
intermixed with parameters, so now if a multi-token parameter
value is encountered, the first word is taken as the value and
the remaining words are ignored, generating a warning message.
Since I have no idea what these values are used for, I cannot say
with certainty whether or not this would break LVS, but in the
test case given to me, the parameter had no impact on LVS, but
was apparently an annotation for the layout editor.
ifndef, endif conditional statements. Pre-define the key "LVS"
for use with netgen. Also corrected some problems stemming from
the way delimiters are handled and the flexible use of whitespace
in verilog.
be in any specific order since all ports are named. Also corrected
problem with pin names not using the same string matching function
as used for nets in general (which affects the ability to match
against different bus delimiters).
Tim Edwards
Tim Edwards