Fischer Moseley ecfbdaa86b cli: remove JSON loader, add test for instantiation generation		2024-10-08 11:42:10 -06:00
..
test_bridge_rx_sim.py	meta: move to lib.io and lib.mem, enable bidirectional mem tests on xilinx	2024-07-17 18:51:05 -07:00
test_bridge_tx_sim.py	meta: move to lib.io and lib.mem, enable bidirectional mem tests on xilinx	2024-07-17 18:51:05 -07:00
test_config_export.py	meta: expose Amaranth API via __all__	2024-10-08 11:42:10 -06:00
test_examples_build.py	tests: include building examples in test suite	2024-10-08 11:42:10 -06:00
test_io_core_hw.py	meta: expose Amaranth API via __all__	2024-10-08 11:42:10 -06:00
test_io_core_sim.py	meta: expose Amaranth API via __all__	2024-10-08 11:42:10 -06:00
test_logic_analyzer_fsm_sim.py	tests: refactor to use Amaranth-native API	2024-10-08 11:42:10 -06:00
test_logic_analyzer_hw.py	meta: expose Amaranth API via __all__	2024-10-08 11:42:10 -06:00
test_logic_analyzer_sim.py	meta: expose Amaranth API via __all__	2024-10-08 11:42:10 -06:00
test_mem_core_hw.py	meta: expose Amaranth API via __all__	2024-10-08 11:42:10 -06:00
test_mem_core_sim.py	tests: refactor to use Amaranth-native API	2024-10-08 11:42:10 -06:00
test_source_bridge_sim.py	meta: expose Amaranth API via __all__	2024-10-08 11:42:10 -06:00
test_toolchains.py	rename Nexys A7 to Nexys 4 DDR	2024-05-12 10:35:18 -07:00
test_uart_rx_sim.py	meta: move to lib.io and lib.mem, enable bidirectional mem tests on xilinx	2024-07-17 18:51:05 -07:00
test_uart_tx_sim.py	meta: move to lib.io and lib.mem, enable bidirectional mem tests on xilinx	2024-07-17 18:51:05 -07:00
test_verilog_gen.py	cli: remove JSON loader, add test for instantiation generation	2024-10-08 11:42:10 -06:00
test_verilog_gen.yaml	inital source, imported from splat	2023-12-28 14:22:29 -08:00