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__init__.py
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add ability to autodetect serial port
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2023-03-23 20:46:49 -04:00 |
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__main__.py
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add linting to makefile, update bus testbenches
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2023-03-14 16:24:56 -04:00 |
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bit_fifo.v
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add working example for macOS bug
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2023-03-14 16:24:56 -04:00 |
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bridge_rx.v
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clean up testbenches, add Makefile for sims
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2023-03-14 16:24:56 -04:00 |
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bridge_tx.v
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clean up testbenches, add Makefile for sims
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2023-03-14 16:24:56 -04:00 |
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fifo.v
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refactor logic analyzer into submodules
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2023-03-15 22:43:21 -04:00 |
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io_core.v
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paritally imnplement io core autogeneration
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2023-03-16 09:38:17 -04:00 |
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la_fsm.v
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refactor logic analyzer into submodules
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2023-03-15 22:43:21 -04:00 |
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logic_analyzer.v
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refactor logic analyzer into submodules
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2023-03-15 22:43:21 -04:00 |
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lut_ram.v
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rename lut mem to lut ram, add to manta generator
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2023-03-14 16:24:56 -04:00 |
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rx_uart.v
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replace uart modules with zipcpu for testing, TX seems to misalign itself
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2023-03-14 16:24:56 -04:00 |
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sample_mem.v
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refactor logic analyzer into submodules
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2023-03-15 22:43:21 -04:00 |
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trigger.v
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add initialls logic_analyzer core
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2023-03-15 15:57:42 -04:00 |
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trigger_block.v
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refactor logic analyzer into submodules
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2023-03-15 22:43:21 -04:00 |
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tx_uart.v
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replace uart modules with zipcpu for testing, TX seems to misalign itself
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2023-03-14 16:24:56 -04:00 |
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uart_tx.v
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add module definitions to generated hdl
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2023-03-14 16:24:56 -04:00 |
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xilinx_true_dual_port_read_first_2_clock_ram.v
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clean up testbenches, add Makefile for sims
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2023-03-14 16:24:56 -04:00 |
a562c8136c