Fischer Moseley a562c8136c add ability to autodetect serial port

2023-03-23 20:46:49 -04:00

..

__init__.py

add ability to autodetect serial port

2023-03-23 20:46:49 -04:00

__main__.py

add linting to makefile, update bus testbenches

2023-03-14 16:24:56 -04:00

bit_fifo.v

add working example for macOS bug

2023-03-14 16:24:56 -04:00

bridge_rx.v

clean up testbenches, add Makefile for sims

2023-03-14 16:24:56 -04:00

bridge_tx.v

clean up testbenches, add Makefile for sims

2023-03-14 16:24:56 -04:00

fifo.v

refactor logic analyzer into submodules

2023-03-15 22:43:21 -04:00

io_core.v

paritally imnplement io core autogeneration

2023-03-16 09:38:17 -04:00

la_fsm.v

refactor logic analyzer into submodules

2023-03-15 22:43:21 -04:00

logic_analyzer.v

refactor logic analyzer into submodules

2023-03-15 22:43:21 -04:00

lut_ram.v

rename lut mem to lut ram, add to manta generator

2023-03-14 16:24:56 -04:00

rx_uart.v

replace uart modules with zipcpu for testing, TX seems to misalign itself

2023-03-14 16:24:56 -04:00

sample_mem.v

refactor logic analyzer into submodules

2023-03-15 22:43:21 -04:00

trigger_block.v

refactor logic analyzer into submodules

2023-03-15 22:43:21 -04:00

trigger.v

add initialls logic_analyzer core

2023-03-15 15:57:42 -04:00

tx_uart.v

replace uart modules with zipcpu for testing, TX seems to misalign itself

2023-03-14 16:24:56 -04:00

uart_tx.v

add module definitions to generated hdl

2023-03-14 16:24:56 -04:00

xilinx_true_dual_port_read_first_2_clock_ram.v

clean up testbenches, add Makefile for sims

2023-03-14 16:24:56 -04:00