Fischer Moseley 12f498dc9a add cursed BRAM core implementation		2023-04-10 14:38:29 -04:00
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bit_fifo_tb	remove all narly verilog from python! 🤠	2023-04-08 16:23:02 -04:00
bram_core_tb	add cursed BRAM core implementation	2023-04-10 14:38:29 -04:00
io_core_tb	update makefile to represent new functional sim locations	2023-04-09 22:33:58 -04:00
logic_analyzer_tb	remove all narly verilog from python! 🤠	2023-04-08 16:23:02 -04:00
bridge_rx_tb.sv	clean up inferred BRAM, trim whitespace	2023-04-03 21:20:58 -04:00
bridge_tx_tb.sv	clean up inferred BRAM, trim whitespace	2023-04-03 21:20:58 -04:00
bus_fix_tb.sv	clean up inferred BRAM, trim whitespace	2023-04-03 21:20:58 -04:00
lut_ram_tb.sv	clean up inferred BRAM, trim whitespace	2023-04-03 21:20:58 -04:00
uart_tb.sv	refactor test structure	2023-04-02 20:33:50 -04:00
uart_tx_tb.sv	clean up inferred BRAM, trim whitespace	2023-04-03 21:20:58 -04:00