Fischer Moseley
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12f498dc9a
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add cursed BRAM core implementation
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2023-04-10 14:38:29 -04:00 |
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Fischer Moseley
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1710da6f87
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update makefile to represent new functional sim locations
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2023-04-09 22:33:58 -04:00 |
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Fischer Moseley
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353be7551e
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remove all narly verilog from python! 🤠
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2023-04-08 16:23:02 -04:00 |
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Fischer Moseley
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c604614428
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autogenerate logic_analyzer and sample_mem
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2023-04-03 23:15:09 -04:00 |
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Fischer Moseley
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0a4a1519c4
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clean up inferred BRAM, trim whitespace
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2023-04-03 21:20:58 -04:00 |
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Fischer Moseley
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8f08dffc70
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consolidate logic analyzer testbench
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2023-04-03 12:20:24 -04:00 |
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Fischer Moseley
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df4d243b9a
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refactor test structure
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2023-04-02 20:33:50 -04:00 |