Fischer Moseley
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dffc503d91
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io_core: use 32-bit data words
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2026-03-28 21:44:03 -06:00 |
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Fischer Moseley
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03975d6f30
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ethernet: fix off-by-one bug in bridge
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2026-03-28 21:08:22 -06:00 |
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Fischer Moseley
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4018779b85
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memory_core: update tests to use 32-bit words
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2026-03-28 20:19:01 -06:00 |
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Fischer Moseley
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f8690176e7
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mem_core: update tests for 32-bit data words
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2026-03-28 20:14:49 -06:00 |
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Fischer Moseley
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0118232555
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tests: use pytest-randomly for reproducible randomness
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2026-03-28 20:14:49 -06:00 |
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Fischer Moseley
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9df707b483
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uart: remove superceded uart_bridge_sim test
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2026-03-28 20:14:49 -06:00 |
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Fischer Moseley
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06fa7a3ace
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uart: use new datapath, reimplement read/write methods, revert to old connectivity approach
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2026-03-28 20:14:47 -06:00 |
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Fischer Moseley
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b70aff9ad4
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uart: fix (another) bit-slicing bug in StreamUnpacker
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2026-03-28 20:13:31 -06:00 |
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Fischer Moseley
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4a60a848a4
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meta: remove unneeded last signal from internal bus
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2026-03-28 20:13:31 -06:00 |
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Fischer Moseley
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a7bd7d20b2
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meta: use InternalBusLayout instead of InternalBus()
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2026-03-28 20:13:31 -06:00 |
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Fischer Moseley
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f61b4ca2b6
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uart: add full datapath test
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2026-03-28 20:13:31 -06:00 |
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Fischer Moseley
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018f7cc223
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uart: rewrite bridge to support backpressure on output
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2026-03-28 20:13:31 -06:00 |
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Fischer Moseley
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de42bf98f4
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uart: fix bit-slicing bug in StreamUnpacker
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2026-03-28 20:13:31 -06:00 |
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Fischer Moseley
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f64107d0c9
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uart: add random COBS decoder tests
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2026-03-28 20:13:31 -06:00 |
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Fischer Moseley
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6fb3997c0d
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uart: COBS decoder working with both irritators
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2026-03-28 20:13:31 -06:00 |
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Fischer Moseley
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34b52f06c2
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uart: initial commit of updated COBS decoder
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2026-03-28 20:13:31 -06:00 |
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Fischer Moseley
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f3e4329fd1
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meta: add cobs package to pyproject.toml dependencies and re-lock
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2026-03-28 20:13:31 -06:00 |
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Fischer Moseley
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ca81ceff89
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meta: autoformat with updated ruff config
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2026-03-28 20:13:31 -06:00 |
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Fischer Moseley
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68740fb34b
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uart: add more cases to random COBS encoder tests
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2026-03-28 20:13:31 -06:00 |
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Fischer Moseley
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e1ead7c3ae
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uart: tidy COBS encoder tests
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2026-03-28 20:13:31 -06:00 |
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Fischer Moseley
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e7306e51c8
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uart: fix COBS encoder bug where 254th byte is zero
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2026-03-28 20:13:31 -06:00 |
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Fischer Moseley
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29f8603728
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uart: handle case of 255 byte-long groups in COBS encoder
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2026-03-28 20:13:31 -06:00 |
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Fischer Moseley
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6a2aed2c8a
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uart: rewrite COBS encoder to allow backpressure
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2026-03-28 20:13:31 -06:00 |
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Fischer Moseley
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54639ccbec
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uart: use wiring.Component for internal bus
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2026-03-28 20:13:24 -06:00 |
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Fischer Moseley
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0c77b9e49a
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uart: remove unused bridge testbenches
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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1714521026
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uart: fix tests for receiver and transmitter modules
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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e4f6f29b05
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uart: update top-level wiring in UARTInterface
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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45aa34ffc0
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uart: remove unused receive and transmit bridges
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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43c22aa0e5
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uart: use wiring.Component instead of plain Elaborateable
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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6b4db337dc
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uart: implement stream (un)packing, tidy interfaces on COBS encoder
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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db81d8cbf0
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meta: replace Signal(1) with Signal()
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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498ab321f3
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uart: add skeleton of new UART RTL, add COBS from fischermoseley/cobs
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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61e7d2e961
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ethernet: remove obsolete tests, fix naming
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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ca3605cb81
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logic_analyzer: use read_block when dumping sample memory for performance
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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acaade9eb5
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ethernet: remove debug print statement
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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d6b2b4ec78
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memory_core: use 32-bit instead of 16-bit data words
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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8d319e9e76
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ethernet: use context manager to read generated LiteEth Verilog
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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5d614127cf
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ethernet: fix host-side UDP socket leak
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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35c981c4f2
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logic_analyzer: use context manager for VCD file export
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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8aeef78ec6
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logic_analyzer: fix 100% CPU wait loop in capture function
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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e415f2b733
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ethernet: use EthernetMessageHeader class
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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26b8598143
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ethernet: fix host-side perf bug causing unneccesary retransmits
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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ea2f1a04e6
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ethernet: fix bug where single-length write request does not send response
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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96daa57279
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ethernet: send write reponses, fix write request addressing bug
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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7f6bf5a3cc
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ethernet: rewrite read and write methods, fix data ordering bug
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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cdc611f88d
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ethernet: bugfix in read transmit logic
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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030011c1cb
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ethernet: use new bridge in EthernetInterface
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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d5300a3daa
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ethernet: add first draft of new bridge
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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b928ea2a60
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docs: add --locked to uv sync instructions
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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62297a8474
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ci: update path to Vivado binary
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2026-03-17 11:22:37 -06:00 |