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ethernet: fix off-by-one bug in bridge

This commit is contained in:
Fischer Moseley 2026-03-28 21:08:22 -06:00
parent 4018779b85
commit 03975d6f30
1 changed files with 6 additions and 4 deletions
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10
src/manta/ethernet/bridge.py
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@ -18,6 +18,7 @@ class EthernetBridge(wiring.Component):
msg_type = Signal(MessageTypes)
seq_num_expected = Signal(13)
seen_first = Signal()
seen_last = Signal()
count = Signal(7)
@ -67,19 +68,19 @@ class EthernetBridge(wiring.Component):
# Once that hits zero and seen_last is high, we're done!
# Send write response and wait for it to clock out
m.d.sync += seen_last.eq(
seen_last | (self.sink.last & self.sink.valid & self.sink.ready)
)
m.d.sync += count.eq(
count + (self.sink.valid & self.sink.ready) - self.bus_sink.p.valid
)
with m.If(self.sink.valid & self.sink.ready):
m.d.sync += self.bus_source.p.addr.eq(self.bus_source.p.addr + 1)
m.d.sync += self.bus_source.p.addr.eq(self.bus_source.p.addr + seen_first)
m.d.sync += self.bus_source.p.data.eq(self.sink.data)
m.d.sync += self.bus_source.p.rw.eq(1)
m.d.sync += self.bus_source.p.valid.eq(1)
m.d.sync += seen_first.eq(1)
m.d.sync += seen_last.eq(seen_last | self.sink.last)
with m.Else():
m.d.sync += self.bus_source.p.data.eq(0) # just for clarity of debugging
m.d.sync += self.bus_source.p.rw.eq(0) # just for clarity of debugging
@ -90,6 +91,7 @@ class EthernetBridge(wiring.Component):
m.d.sync += self.source.valid.eq(0)
m.d.sync += self.source.last.eq(0) # just for clarity of debugging
m.d.sync += self.source.data.eq(0) # just for clarity of debugging
m.d.sync += seen_first.eq(0)
m.next = "IDLE"
with m.Else():