Fischer Moseley
|
d63ce8305b
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uart: add more cases to random COBS encoder tests
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
|
349de40cd2
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uart: tidy COBS encoder tests
|
2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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d8fbf71146
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uart: fix COBS encoder bug where 254th byte is zero
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
|
0c0f6121b3
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uart: handle case of 255 byte-long groups in COBS encoder
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
|
6631ddde6a
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uart: rewrite COBS encoder to allow backpressure
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
|
b1fc256f26
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uart: use wiring.Component for internal bus
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
|
0c77b9e49a
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uart: remove unused bridge testbenches
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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1714521026
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uart: fix tests for receiver and transmitter modules
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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e4f6f29b05
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uart: update top-level wiring in UARTInterface
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
|
45aa34ffc0
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uart: remove unused receive and transmit bridges
|
2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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43c22aa0e5
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uart: use wiring.Component instead of plain Elaborateable
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2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
6b4db337dc
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uart: implement stream (un)packing, tidy interfaces on COBS encoder
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
|
db81d8cbf0
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meta: replace Signal(1) with Signal()
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2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
498ab321f3
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uart: add skeleton of new UART RTL, add COBS from fischermoseley/cobs
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
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61e7d2e961
|
ethernet: remove obsolete tests, fix naming
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
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ca3605cb81
|
logic_analyzer: use read_block when dumping sample memory for performance
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
acaade9eb5
|
ethernet: remove debug print statement
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
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d6b2b4ec78
|
memory_core: use 32-bit instead of 16-bit data words
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
8d319e9e76
|
ethernet: use context manager to read generated LiteEth Verilog
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
5d614127cf
|
ethernet: fix host-side UDP socket leak
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
35c981c4f2
|
logic_analyzer: use context manager for VCD file export
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
8aeef78ec6
|
logic_analyzer: fix 100% CPU wait loop in capture function
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
e415f2b733
|
ethernet: use EthernetMessageHeader class
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
26b8598143
|
ethernet: fix host-side perf bug causing unneccesary retransmits
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
ea2f1a04e6
|
ethernet: fix bug where single-length write request does not send response
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
96daa57279
|
ethernet: send write reponses, fix write request addressing bug
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
7f6bf5a3cc
|
ethernet: rewrite read and write methods, fix data ordering bug
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
cdc611f88d
|
ethernet: bugfix in read transmit logic
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
030011c1cb
|
ethernet: use new bridge in EthernetInterface
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
d5300a3daa
|
ethernet: add first draft of new bridge
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
b928ea2a60
|
docs: add --locked to uv sync instructions
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
62297a8474
|
ci: update path to Vivado binary
|
2026-03-17 11:22:37 -06:00 |
|
Fischer Moseley
|
3c67eaf399
|
examples: use symlinked build scripts, remove per-directory gitignores
|
2026-03-11 10:20:17 -06:00 |
|
Fischer Moseley
|
6e6cd6bfd7
|
CI: manage environment with uv
|
2026-02-25 14:57:38 -07:00 |
|
Fischer Moseley
|
1e5a247cf4
|
meta: set ruff max line length to 100 characters
This should hopefully make the Amaranth source more readable, since indentation and the `m.d.sync +=` prefix take a bit of line space.
|
2026-02-25 13:18:23 -07:00 |
|
Fischer Moseley
|
40d428614b
|
meta: add uv.lock, update installation instructions
|
2026-02-25 13:18:23 -07:00 |
|
Fischer Moseley
|
cc8e7bb08b
|
meta: use amaranth-boards from PyPI, not git
|
2026-02-25 13:18:23 -07:00 |
|
Fischer Moseley
|
10593c768e
|
logic_analyzer: fix #35, patch typos in trigger set logic
|
2025-04-08 11:18:44 -06:00 |
|
Fischer Moseley
|
b9a7e75355
|
examples: fix #37, use proper indexing in Amaranth examples
|
2025-04-06 20:15:08 -06:00 |
|
Fischer Moseley
|
9611c0b554
|
uart: fix #36, explicitly handle scientific notation in YAML config
|
2025-04-06 18:28:29 -06:00 |
|
Fischer Moseley
|
e11d9a8315
|
ci: fix typo
|
2024-12-03 22:35:16 -08:00 |
|
Fischer Moseley
|
5565a934f7
|
docs: use absolute logo path
|
2024-12-03 20:05:26 -08:00 |
|
Fischer Moseley
|
91d2f80dcc
|
meta: update pyproject.toml
|
2024-12-03 19:50:04 -08:00 |
|
Fischer Moseley
|
77b329438a
|
ci: remove unnecessary codecov.yml
|
2024-11-29 11:05:47 -07:00 |
|
Fischer Moseley
|
63efac4e92
|
ci: install manta in editable mode
|
2024-11-29 11:05:47 -07:00 |
|
Fischer Moseley
|
38808b9e5e
|
ci: show coverage report in CI, explicitly specify test directory
|
2024-11-29 11:05:47 -07:00 |
|
Fischer Moseley
|
0fb3cb0418
|
ci: explicitly specify src/ as coverage directory
|
2024-11-29 11:05:47 -07:00 |
|
Fischer Moseley
|
eddfa0bf6b
|
ci: generate XML coverage report for codecov
|
2024-11-29 11:05:47 -07:00 |
|
Fischer Moseley
|
7015be8fe9
|
meta: update package name on PyPI
|
2024-11-28 09:40:40 -08:00 |
|
Fischer Moseley
|
1e9e7081ed
|
docs: update package name in installation instructions
|
2024-11-27 21:30:12 -08:00 |