Fischer Moseley
|
a11b36a887
|
uart: remove superceded uart_bridge_sim test
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
032ff1929f
|
uart: use new datapath, reimplement read/write methods, revert to old connectivity approach
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
d58f22212a
|
uart: fix (another) bit-slicing bug in StreamUnpacker
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
eb3a9d691f
|
meta: remove unneeded last signal from internal bus
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
06584a44c1
|
meta: use InternalBusLayout instead of InternalBus()
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
051cf460fa
|
uart: add full datapath test
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
5fc41b5c70
|
uart: rewrite bridge to support backpressure on output
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
5ca0e43a94
|
uart: fix bit-slicing bug in StreamUnpacker
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
8019aecf59
|
uart: add random COBS decoder tests
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
aa0429763c
|
uart: COBS decoder working with both irritators
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
a67adc31d2
|
uart: initial commit of updated COBS decoder
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
89837007eb
|
meta: add cobs package to pyproject.toml dependencies and re-lock
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
e82f0ab6e8
|
meta: autoformat with updated ruff config
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
d63ce8305b
|
uart: add more cases to random COBS encoder tests
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
349de40cd2
|
uart: tidy COBS encoder tests
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
d8fbf71146
|
uart: fix COBS encoder bug where 254th byte is zero
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
0c0f6121b3
|
uart: handle case of 255 byte-long groups in COBS encoder
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
6631ddde6a
|
uart: rewrite COBS encoder to allow backpressure
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
b1fc256f26
|
uart: use wiring.Component for internal bus
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
0c77b9e49a
|
uart: remove unused bridge testbenches
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
1714521026
|
uart: fix tests for receiver and transmitter modules
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
e4f6f29b05
|
uart: update top-level wiring in UARTInterface
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
45aa34ffc0
|
uart: remove unused receive and transmit bridges
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
43c22aa0e5
|
uart: use wiring.Component instead of plain Elaborateable
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
6b4db337dc
|
uart: implement stream (un)packing, tidy interfaces on COBS encoder
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
db81d8cbf0
|
meta: replace Signal(1) with Signal()
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
498ab321f3
|
uart: add skeleton of new UART RTL, add COBS from fischermoseley/cobs
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
61e7d2e961
|
ethernet: remove obsolete tests, fix naming
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
ca3605cb81
|
logic_analyzer: use read_block when dumping sample memory for performance
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
acaade9eb5
|
ethernet: remove debug print statement
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
d6b2b4ec78
|
memory_core: use 32-bit instead of 16-bit data words
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
8d319e9e76
|
ethernet: use context manager to read generated LiteEth Verilog
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
5d614127cf
|
ethernet: fix host-side UDP socket leak
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
35c981c4f2
|
logic_analyzer: use context manager for VCD file export
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
8aeef78ec6
|
logic_analyzer: fix 100% CPU wait loop in capture function
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
e415f2b733
|
ethernet: use EthernetMessageHeader class
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
26b8598143
|
ethernet: fix host-side perf bug causing unneccesary retransmits
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
ea2f1a04e6
|
ethernet: fix bug where single-length write request does not send response
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
96daa57279
|
ethernet: send write reponses, fix write request addressing bug
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
7f6bf5a3cc
|
ethernet: rewrite read and write methods, fix data ordering bug
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
cdc611f88d
|
ethernet: bugfix in read transmit logic
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
030011c1cb
|
ethernet: use new bridge in EthernetInterface
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
d5300a3daa
|
ethernet: add first draft of new bridge
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
b928ea2a60
|
docs: add --locked to uv sync instructions
|
2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
|
62297a8474
|
ci: update path to Vivado binary
|
2026-03-17 11:22:37 -06:00 |
|
Fischer Moseley
|
3c67eaf399
|
examples: use symlinked build scripts, remove per-directory gitignores
|
2026-03-11 10:20:17 -06:00 |
|
Fischer Moseley
|
6e6cd6bfd7
|
CI: manage environment with uv
|
2026-02-25 14:57:38 -07:00 |
|
Fischer Moseley
|
1e5a247cf4
|
meta: set ruff max line length to 100 characters
This should hopefully make the Amaranth source more readable, since indentation and the `m.d.sync +=` prefix take a bit of line space.
|
2026-02-25 13:18:23 -07:00 |
|
Fischer Moseley
|
40d428614b
|
meta: add uv.lock, update installation instructions
|
2026-02-25 13:18:23 -07:00 |
|
Fischer Moseley
|
cc8e7bb08b
|
meta: use amaranth-boards from PyPI, not git
|
2026-02-25 13:18:23 -07:00 |