Fischer Moseley
|
8a497aaf1f
|
meta: replace Signal(1) with Signal()
|
2026-02-25 15:02:15 -07:00 |
Fischer Moseley
|
3f55a57f5b
|
uart: add skeleton of new UART RTL, add COBS from fischermoseley/cobs
|
2026-02-25 15:02:15 -07:00 |
Fischer Moseley
|
1d5c59cfa7
|
ethernet: remove obsolete tests, fix naming
|
2026-02-25 15:02:15 -07:00 |
Fischer Moseley
|
87073086a6
|
logic_analyzer: use read_block when dumping sample memory for performance
|
2026-02-25 15:02:15 -07:00 |
Fischer Moseley
|
ccd016f3d4
|
ethernet: remove debug print statement
|
2026-02-25 15:02:15 -07:00 |
Fischer Moseley
|
7fca0bf5f0
|
memory_core: use 32-bit instead of 16-bit data words
|
2026-02-25 15:02:15 -07:00 |
Fischer Moseley
|
a1c7d194e8
|
ethernet: use context manager to read generated LiteEth Verilog
|
2026-02-25 15:02:15 -07:00 |
Fischer Moseley
|
6aea352fba
|
ethernet: fix host-side UDP socket leak
|
2026-02-25 15:02:15 -07:00 |
Fischer Moseley
|
82f289aa74
|
logic_analyzer: use context manager for VCD file export
|
2026-02-25 15:02:15 -07:00 |
Fischer Moseley
|
fef4f83c3d
|
logic_analyzer: fix 100% CPU wait loop in capture function
|
2026-02-25 15:02:15 -07:00 |
Fischer Moseley
|
470244966d
|
gitignore: tidy and remove unnecessary per-directory gitignores
|
2026-02-25 15:02:15 -07:00 |
Fischer Moseley
|
e7f7f89494
|
examples: check for tool availability before building
|
2026-02-25 15:02:15 -07:00 |
Fischer Moseley
|
9640d7db3e
|
examples: use symlinked bash and Tcl scripts
|
2026-02-25 15:02:15 -07:00 |
Fischer Moseley
|
3712c55032
|
ethernet: use EthernetMessageHeader class
|
2026-02-25 15:02:15 -07:00 |
Fischer Moseley
|
11c1e47724
|
ethernet: fix host-side perf bug causing unneccesary retransmits
|
2026-02-25 15:02:15 -07:00 |
Fischer Moseley
|
b17220a36d
|
ethernet: fix bug where single-length write request does not send response
|
2026-02-25 15:02:15 -07:00 |
Fischer Moseley
|
ffc3829968
|
ethernet: send write reponses, fix write request addressing bug
|
2026-02-25 15:02:15 -07:00 |
Fischer Moseley
|
38de74c703
|
ethernet: rewrite read and write methods, fix data ordering bug
|
2026-02-25 15:02:15 -07:00 |
Fischer Moseley
|
0c778e1678
|
ethernet: bugfix in read transmit logic
|
2026-02-25 15:02:15 -07:00 |
Fischer Moseley
|
209eb8e6f7
|
ethernet: use new bridge in EthernetInterface
|
2026-02-25 15:02:15 -07:00 |
Fischer Moseley
|
5e6ea212a4
|
ethernet: add first draft of new bridge
|
2026-02-25 15:02:15 -07:00 |
Fischer Moseley
|
c64f4b0191
|
meta: rename environment.sh to .env, add nextpnr-gowin
|
2026-02-25 15:02:13 -07:00 |
Fischer Moseley
|
6e6cd6bfd7
|
CI: manage environment with uv
|
2026-02-25 14:57:38 -07:00 |
Fischer Moseley
|
1e5a247cf4
|
meta: set ruff max line length to 100 characters
This should hopefully make the Amaranth source more readable, since indentation and the `m.d.sync +=` prefix take a bit of line space.
|
2026-02-25 13:18:23 -07:00 |
Fischer Moseley
|
40d428614b
|
meta: add uv.lock, update installation instructions
|
2026-02-25 13:18:23 -07:00 |
Fischer Moseley
|
cc8e7bb08b
|
meta: use amaranth-boards from PyPI, not git
|
2026-02-25 13:18:23 -07:00 |
Fischer Moseley
|
10593c768e
|
logic_analyzer: fix #35, patch typos in trigger set logic
|
2025-04-08 11:18:44 -06:00 |
Fischer Moseley
|
b9a7e75355
|
examples: fix #37, use proper indexing in Amaranth examples
|
2025-04-06 20:15:08 -06:00 |
Fischer Moseley
|
9611c0b554
|
uart: fix #36, explicitly handle scientific notation in YAML config
|
2025-04-06 18:28:29 -06:00 |
Fischer Moseley
|
e11d9a8315
|
ci: fix typo
|
2024-12-03 22:35:16 -08:00 |
Fischer Moseley
|
5565a934f7
|
docs: use absolute logo path
|
2024-12-03 20:05:26 -08:00 |
Fischer Moseley
|
91d2f80dcc
|
meta: update pyproject.toml
|
2024-12-03 19:50:04 -08:00 |
Fischer Moseley
|
77b329438a
|
ci: remove unnecessary codecov.yml
|
2024-11-29 11:05:47 -07:00 |
Fischer Moseley
|
63efac4e92
|
ci: install manta in editable mode
|
2024-11-29 11:05:47 -07:00 |
Fischer Moseley
|
38808b9e5e
|
ci: show coverage report in CI, explicitly specify test directory
|
2024-11-29 11:05:47 -07:00 |
Fischer Moseley
|
0fb3cb0418
|
ci: explicitly specify src/ as coverage directory
|
2024-11-29 11:05:47 -07:00 |
Fischer Moseley
|
eddfa0bf6b
|
ci: generate XML coverage report for codecov
|
2024-11-29 11:05:47 -07:00 |
Fischer Moseley
|
7015be8fe9
|
meta: update package name on PyPI
|
2024-11-28 09:40:40 -08:00 |
Fischer Moseley
|
1e9e7081ed
|
docs: update package name in installation instructions
|
2024-11-27 21:30:12 -08:00 |
Fischer Moseley
|
f43732354d
|
meta: fix coverage path
|
2024-11-27 20:56:20 -08:00 |
Fischer Moseley
|
cb7e1e4c2a
|
meta: bump version to 1.1.0 ahead of release
|
2024-11-27 18:17:30 -08:00 |
Fischer Moseley
|
56223132c0
|
ci: run pre-commit on all files in CI
|
2024-11-27 19:10:52 -07:00 |
Fischer Moseley
|
f91f7c5fbb
|
meta: add pre-commit, commit changes it makes
|
2024-11-27 19:10:52 -07:00 |
Fischer Moseley
|
5759da568d
|
tests: remove redundant test_toolchains test
|
2024-11-27 19:10:52 -07:00 |
Fischer Moseley
|
9937269c19
|
ethernet: add individual methods for each flavor of MII
|
2024-11-27 19:10:52 -07:00 |
Fischer Moseley
|
a80bd399e7
|
examples: determine divider.sv path at runtime
|
2024-11-27 19:10:52 -07:00 |
Fischer Moseley
|
ccecc16726
|
ethernet: fix path to divider.sv
|
2024-11-27 19:10:52 -07:00 |
Fischer Moseley
|
da21a3a414
|
ethernet: load divider.sv via symlink
|
2024-11-27 19:10:52 -07:00 |
Fischer Moseley
|
363bef8d87
|
ethernet: add HWITL ethernet test
|
2024-11-27 19:10:52 -07:00 |
Fischer Moseley
|
2761507803
|
tests: add ethernet_io_core to build_examples test
|
2024-11-27 19:10:52 -07:00 |