examples: use symlinked bash and Tcl scripts

examples/common/build.tcl

@@ -0,0 +1,35 @@
+#!/usr/bin/tclsh
+
+set partNum xc7a100tcsg324-1
+
+read_verilog -sv [ glob ../*.{sv,v,svh,vh} ]
+read_xdc ../top_level.xdc
+
+set_part $partNum
+
+# synth
+synth_design -top top_level -part $partNum -verbose
+report_utilization -file post_synth_util.rpt
+report_timing_summary -file post_synth_timing_summary.rpt
+report_timing -file post_synth_timing.rpt
+
+# place
+opt_design
+place_design
+phys_opt_design
+report_utilization -file post_place_util.rpt
+
+report_clock_utilization -file clock_util.rpt
+report_timing_summary -file post_place_timing_summary.rpt
+report_timing -file post_place_timing.rpt
+
+# route design and generate bitstream
+route_design -directive Explore
+write_bitstream -force out.bit
+
+report_route_status -file post_route_status.rpt
+report_timing_summary -file post_route_timing_summary.rpt
+report_timing -file post_route_timing.rpt
+report_power -file post_route_power.rpt
+report_drc -file post_imp_drc.rpt
+write_verilog -force cpu_impl_netlist.v -mode timesim -sdf_anno true

examples/common/build_ice40.sh

@@ -0,0 +1,13 @@
+#!/usr/bin/env bash
+set -euo pipefail
+
+# Generate Verilog source for Manta
+python3 -m manta gen manta.yaml manta.v
+
+# Clean build/ directory, and run tools from within it
+rm -rf build/
+mkdir -p build/
+cd build
+$YOSYS -p 'synth_ice40 -top top_level -json top_level.json' ../top_level.sv
+$NEXTPNR_ICE40 --hx1k --json top_level.json --pcf ../top_level.pcf --asc top_level.asc
+$ICEPACK top_level.asc top_level.bin

examples/common/build_vivado.sh

@@ -0,0 +1,35 @@
+#!/usr/bin/env bash
+set -euo pipefail
+
+# Generate Verilog source for Manta
+python3 -m manta gen manta.yaml manta.v
+
+# Determine where Vivado is located - exactly one of PATH or $VIVADO must be available
+vivado_on_path=false
+vivado_env_set=false
+
+if command -v vivado &> /dev/null; then
+    vivado_on_path=true
+fi
+
+if [[ -v VIVADO ]]; then
+    vivado_env_set=true
+fi
+
+if $vivado_on_path && $vivado_env_set; then
+    echo "Error: Both \$VIVADO is set and 'vivado' is on PATH. Please use only one." >&2
+    exit 1
+elif $vivado_on_path; then
+    VIVADO_CMD="vivado"
+elif $vivado_env_set; then
+    VIVADO_CMD="$VIVADO"
+else
+    echo "Error: Vivado not found. Either set \$VIVADO environment variable or add 'vivado' to PATH." >&2
+    exit 1
+fi
+
+# Clean build/ directory, and run Vivado from within it
+rm -rf build/
+mkdir -p build/
+cd build
+$VIVADO_CMD -mode batch -source ../../../../common/build.tcl

examples/verilog/icestick/uart_io_core/build.sh

@@ -1,7 +0,0 @@
-#!/usr/bin/env bash
-set -e
-
-python3 -m manta gen manta.yaml manta.v
-$YOSYS -p 'synth_ice40 -top top_level -json top_level.json' top_level.sv
-$NEXTPNR_ICE40 --hx1k --json top_level.json --pcf top_level.pcf --asc top_level.asc
-$ICEPACK top_level.asc top_level.bin

examples/verilog/icestick/uart_io_core/build.sh

@@ -0,0 +1 @@
+../../../common/build_ice40.sh

examples/verilog/icestick/uart_logic_analyzer/build.sh

@@ -1,7 +0,0 @@
-#!/usr/bin/env bash
-set -e
-
-python3 -m manta gen manta.yaml manta.v
-$YOSYS -p 'synth_ice40 -top top_level -json top_level.json' top_level.sv
-$NEXTPNR_ICE40 --hx1k --json top_level.json --pcf top_level.pcf --asc top_level.asc
-$ICEPACK top_level.asc top_level.bin

examples/verilog/icestick/uart_logic_analyzer/build.sh

@@ -0,0 +1 @@
+../../../common/build_ice40.sh

examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.sh

@@ -1,6 +0,0 @@
-#!/usr/bin/env bash
-set -e
-
-python3 -m manta gen manta.yaml manta.v
-mkdir -p build/
-$VIVADO -mode batch -source build.tcl

examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.sh

@@ -0,0 +1 @@
+../../../common/build_vivado.sh

examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.tcl

@@ -1,36 +0,0 @@
-#!/usr/bin/tclsh
-
-set partNum xc7a100tcsg324-1
-set outputDir build
-
-read_verilog -sv [ glob *.{sv,v,svh,vh} ]
-read_xdc top_level.xdc
-
-set_part $partNum
-
-# synth
-synth_design -top top_level -part $partNum -verbose
-report_utilization -file $outputDir/post_synth_util.rpt
-report_timing_summary -file $outputDir/post_synth_timing_summary.rpt
-report_timing -file $outputDir/post_synth_timing.rpt
-
-# place
-opt_design
-place_design
-phys_opt_design
-report_utilization -file $outputDir/post_place_util.rpt
-
-report_clock_utilization -file $outputDir/clock_util.rpt
-report_timing_summary -file $outputDir/post_place_timing_summary.rpt
-report_timing -file $outputDir/post_place_timing.rpt
-
-# route design and generate bitstream
-route_design -directive Explore
-write_bitstream -force $outputDir/out.bit
-
-report_route_status -file $outputDir/post_route_status.rpt
-report_timing_summary -file $outputDir/post_route_timing_summary.rpt
-report_timing -file $outputDir/post_route_timing.rpt
-report_power -file $outputDir/post_route_power.rpt
-report_drc -file $outputDir/post_imp_drc.rpt
-write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true

examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.sh

@@ -1,6 +0,0 @@
-#!/usr/bin/env bash
-set -e
-
-python3 -m manta gen manta.yaml manta.v
-mkdir -p build/
-$VIVADO -mode batch -source build.tcl

examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.sh

@@ -0,0 +1 @@
+../../../common/build_vivado.sh

examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.tcl

@@ -1,36 +0,0 @@
-#!/usr/bin/tclsh
-
-set partNum xc7a100tcsg324-1
-set outputDir build
-
-read_verilog -sv [ glob *.{sv,v,svh,vh} ]
-read_xdc top_level.xdc
-
-set_part $partNum
-
-# synth
-synth_design -top top_level -part $partNum -verbose
-report_utilization -file $outputDir/post_synth_util.rpt
-report_timing_summary -file $outputDir/post_synth_timing_summary.rpt
-report_timing -file $outputDir/post_synth_timing.rpt
-
-# place
-opt_design
-place_design
-phys_opt_design
-report_utilization -file $outputDir/post_place_util.rpt
-
-report_clock_utilization -file $outputDir/clock_util.rpt
-report_timing_summary -file $outputDir/post_place_timing_summary.rpt
-report_timing -file $outputDir/post_place_timing.rpt
-
-# route design and generate bitstream
-route_design -directive Explore
-write_bitstream -force $outputDir/out.bit
-
-report_route_status -file $outputDir/post_route_status.rpt
-report_timing_summary -file $outputDir/post_route_timing_summary.rpt
-report_timing -file $outputDir/post_route_timing.rpt
-report_power -file $outputDir/post_route_power.rpt
-report_drc -file $outputDir/post_imp_drc.rpt
-write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true

examples/verilog/nexys4_ddr/uart_io_core/build.sh

@@ -1,6 +0,0 @@
-#!/usr/bin/env bash
-set -e
-
-python3 -m manta gen manta.yaml manta.v
-mkdir -p build/
-$VIVADO -mode batch -source build.tcl

examples/verilog/nexys4_ddr/uart_io_core/build.sh

@@ -0,0 +1 @@
+../../../common/build_vivado.sh

examples/verilog/nexys4_ddr/uart_io_core/build.tcl

@@ -1,36 +0,0 @@
-#!/usr/bin/tclsh
-
-set partNum xc7a100tcsg324-1
-set outputDir build
-
-read_verilog -sv [ glob *.{sv,v,svh,vh} ]
-read_xdc top_level.xdc
-
-set_part $partNum
-
-# synth
-synth_design -top top_level -part $partNum -verbose
-report_utilization -file $outputDir/post_synth_util.rpt
-report_timing_summary -file $outputDir/post_synth_timing_summary.rpt
-report_timing -file $outputDir/post_synth_timing.rpt
-
-# place
-opt_design
-place_design
-phys_opt_design
-report_utilization -file $outputDir/post_place_util.rpt
-
-report_clock_utilization -file $outputDir/clock_util.rpt
-report_timing_summary -file $outputDir/post_place_timing_summary.rpt
-report_timing -file $outputDir/post_place_timing.rpt
-
-# route design and generate bitstream
-route_design -directive Explore
-write_bitstream -force $outputDir/out.bit
-
-report_route_status -file $outputDir/post_route_status.rpt
-report_timing_summary -file $outputDir/post_route_timing_summary.rpt
-report_timing -file $outputDir/post_route_timing.rpt
-report_power -file $outputDir/post_route_power.rpt
-report_drc -file $outputDir/post_imp_drc.rpt
-write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true

examples/verilog/nexys4_ddr/uart_logic_analyzer/build.sh

@@ -1,6 +0,0 @@
-#!/usr/bin/env bash
-set -e
-
-python3 -m manta gen manta.yaml manta.v
-mkdir -p build/
-$VIVADO -mode batch -source build.tcl

examples/verilog/nexys4_ddr/uart_logic_analyzer/build.sh

@@ -0,0 +1 @@
+../../../common/build_vivado.sh

examples/verilog/nexys4_ddr/uart_logic_analyzer/build.tcl

@@ -1,36 +0,0 @@
-#!/usr/bin/tclsh
-
-set partNum xc7a100tcsg324-1
-set outputDir build
-
-read_verilog -sv [ glob *.{sv,v,svh,vh} ]
-read_xdc top_level.xdc
-
-set_part $partNum
-
-# synth
-synth_design -top top_level -part $partNum -verbose
-report_utilization -file $outputDir/post_synth_util.rpt
-report_timing_summary -file $outputDir/post_synth_timing_summary.rpt
-report_timing -file $outputDir/post_synth_timing.rpt
-
-# place
-opt_design
-place_design
-phys_opt_design
-report_utilization -file $outputDir/post_place_util.rpt
-
-report_clock_utilization -file $outputDir/clock_util.rpt
-report_timing_summary -file $outputDir/post_place_timing_summary.rpt
-report_timing -file $outputDir/post_place_timing.rpt
-
-# route design and generate bitstream
-route_design -directive Explore
-write_bitstream -force $outputDir/out.bit
-
-report_route_status -file $outputDir/post_route_status.rpt
-report_timing_summary -file $outputDir/post_route_timing_summary.rpt
-report_timing -file $outputDir/post_route_timing.rpt
-report_power -file $outputDir/post_route_power.rpt
-report_drc -file $outputDir/post_imp_drc.rpt
-write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true