Commit Graph

6 Commits

Author SHA1 Message Date
Fischer Moseley 9d8836bda3 add prototype simulation replay 2023-04-17 18:14:31 -04:00
Fischer Moseley ab8582a570 move building examples into makefile, add working logic analyzer test 2023-04-03 23:47:36 -04:00
Fischer Moseley c604614428 autogenerate logic_analyzer and sample_mem 2023-04-03 23:15:09 -04:00
Fischer Moseley ce41d7ec41 clean up inferred BRAM, trim whitespace 2023-04-03 21:20:36 -04:00
Fischer Moseley f682e5386f add working hand-parameterized logic analyzer! still buggy but this is super neato 🤠 2023-04-02 22:49:48 -04:00
Fischer Moseley aa2ba43e8f rename lut mem to lut ram, add to manta generator 2023-03-14 16:24:56 -04:00