Fischer Moseley
|
487b11f155
|
complete refactor to InternalBus()
|
2024-01-07 22:35:15 -08:00 |
|
Fischer Moseley
|
7a6ab45b92
|
revert UART and InternalBus() refactor
|
2024-01-07 21:39:44 -08:00 |
|
Fischer Moseley
|
ee4a3026af
|
refactor to use common bus layout across all modules
|
2024-01-07 18:17:09 -08:00 |
|
Fischer Moseley
|
958ccadbd0
|
refactored logic analyzer working in sim
|
2024-01-05 21:43:53 -08:00 |
|
Fischer Moseley
|
a11605b2b7
|
refactor logic analyzer
|
2024-01-05 16:50:25 -08:00 |
|
Fischer Moseley
|
ee18e10ae1
|
add immediate capture mode to logic analyzer
|
2024-01-03 13:35:09 -07:00 |
|
Fischer Moseley
|
bc616fd3bf
|
inital source, imported from splat
|
2023-12-28 14:22:29 -08:00 |