Fischer Moseley
|
07624d83ee
|
move back to iverilog 13 compatability
|
2023-04-17 18:14:31 -04:00 |
|
Fischer Moseley
|
925fd915be
|
update simulation syntax for iverilog 11 compat
|
2023-04-17 18:14:31 -04:00 |
|
Fischer Moseley
|
1aa067b435
|
update logic_analyzer_tb to use only generated HDL
|
2023-04-17 18:14:31 -04:00 |
|
Fischer Moseley
|
a2ad90a66a
|
modify sim and generator, seems to work in simulation
|
2023-04-17 18:14:31 -04:00 |
|
Fischer Moseley
|
353be7551e
|
remove all narly verilog from python! 🤠
|
2023-04-08 16:23:02 -04:00 |