Fischer Moseley
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ab8582a570
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move building examples into makefile, add working logic analyzer test
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2023-04-03 23:47:36 -04:00 |
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Fischer Moseley
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aab1b5ac10
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add semi-working trigger block autogen
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2023-04-03 16:43:28 -04:00 |
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Fischer Moseley
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ef47b1baf0
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update .gitignore for icestorm output
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2023-04-02 23:19:35 -04:00 |
Fischer Moseley
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f7077f96d8
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add lut ram operations to Python API
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2023-03-23 19:38:19 -04:00 |
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Fischer Moseley
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ca2579e471
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banish .DS_Store
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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70e2bd10e7
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rename, slightly patch bridge_tx
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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ad18b9263b
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i hate python packaging but everything works now
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2023-02-14 20:53:36 -05:00 |
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Fischer Moseley
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02fc53cbf7
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package for PyPI
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2023-02-14 17:14:39 -05:00 |
Fischer Moseley
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e48f60e03a
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make downlink core export as just one verilog file
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2023-02-05 10:22:54 -05:00 |
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Fischer Moseley
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d2bcbe2418
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import from openILA
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2023-02-04 12:43:00 -05:00 |