Fischer Moseley
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0c0f6121b3
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uart: handle case of 255 byte-long groups in COBS encoder
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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6631ddde6a
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uart: rewrite COBS encoder to allow backpressure
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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b1fc256f26
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uart: use wiring.Component for internal bus
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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0c77b9e49a
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uart: remove unused bridge testbenches
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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1714521026
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uart: fix tests for receiver and transmitter modules
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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e4f6f29b05
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uart: update top-level wiring in UARTInterface
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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45aa34ffc0
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uart: remove unused receive and transmit bridges
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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43c22aa0e5
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uart: use wiring.Component instead of plain Elaborateable
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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6b4db337dc
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uart: implement stream (un)packing, tidy interfaces on COBS encoder
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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db81d8cbf0
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meta: replace Signal(1) with Signal()
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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498ab321f3
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uart: add skeleton of new UART RTL, add COBS from fischermoseley/cobs
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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61e7d2e961
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ethernet: remove obsolete tests, fix naming
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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ca3605cb81
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logic_analyzer: use read_block when dumping sample memory for performance
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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acaade9eb5
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ethernet: remove debug print statement
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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d6b2b4ec78
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memory_core: use 32-bit instead of 16-bit data words
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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8d319e9e76
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ethernet: use context manager to read generated LiteEth Verilog
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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5d614127cf
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ethernet: fix host-side UDP socket leak
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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35c981c4f2
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logic_analyzer: use context manager for VCD file export
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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8aeef78ec6
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logic_analyzer: fix 100% CPU wait loop in capture function
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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e415f2b733
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ethernet: use EthernetMessageHeader class
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2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
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26b8598143
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ethernet: fix host-side perf bug causing unneccesary retransmits
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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ea2f1a04e6
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ethernet: fix bug where single-length write request does not send response
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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96daa57279
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ethernet: send write reponses, fix write request addressing bug
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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7f6bf5a3cc
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ethernet: rewrite read and write methods, fix data ordering bug
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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cdc611f88d
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ethernet: bugfix in read transmit logic
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2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
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030011c1cb
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ethernet: use new bridge in EthernetInterface
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2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
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d5300a3daa
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ethernet: add first draft of new bridge
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2026-03-17 11:23:01 -06:00 |
|
Fischer Moseley
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b928ea2a60
|
docs: add --locked to uv sync instructions
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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62297a8474
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ci: update path to Vivado binary
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2026-03-17 11:22:37 -06:00 |
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Fischer Moseley
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3c67eaf399
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examples: use symlinked build scripts, remove per-directory gitignores
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2026-03-11 10:20:17 -06:00 |
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Fischer Moseley
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6e6cd6bfd7
|
CI: manage environment with uv
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2026-02-25 14:57:38 -07:00 |
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Fischer Moseley
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1e5a247cf4
|
meta: set ruff max line length to 100 characters
This should hopefully make the Amaranth source more readable, since indentation and the `m.d.sync +=` prefix take a bit of line space.
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2026-02-25 13:18:23 -07:00 |
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Fischer Moseley
|
40d428614b
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meta: add uv.lock, update installation instructions
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2026-02-25 13:18:23 -07:00 |
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Fischer Moseley
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cc8e7bb08b
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meta: use amaranth-boards from PyPI, not git
|
2026-02-25 13:18:23 -07:00 |
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Fischer Moseley
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10593c768e
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logic_analyzer: fix #35, patch typos in trigger set logic
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2025-04-08 11:18:44 -06:00 |
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Fischer Moseley
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b9a7e75355
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examples: fix #37, use proper indexing in Amaranth examples
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2025-04-06 20:15:08 -06:00 |
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Fischer Moseley
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9611c0b554
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uart: fix #36, explicitly handle scientific notation in YAML config
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2025-04-06 18:28:29 -06:00 |
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Fischer Moseley
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e11d9a8315
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ci: fix typo
|
2024-12-03 22:35:16 -08:00 |
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Fischer Moseley
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5565a934f7
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docs: use absolute logo path
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2024-12-03 20:05:26 -08:00 |
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Fischer Moseley
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91d2f80dcc
|
meta: update pyproject.toml
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2024-12-03 19:50:04 -08:00 |
|
Fischer Moseley
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77b329438a
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ci: remove unnecessary codecov.yml
|
2024-11-29 11:05:47 -07:00 |
|
Fischer Moseley
|
63efac4e92
|
ci: install manta in editable mode
|
2024-11-29 11:05:47 -07:00 |
|
Fischer Moseley
|
38808b9e5e
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ci: show coverage report in CI, explicitly specify test directory
|
2024-11-29 11:05:47 -07:00 |
|
Fischer Moseley
|
0fb3cb0418
|
ci: explicitly specify src/ as coverage directory
|
2024-11-29 11:05:47 -07:00 |
|
Fischer Moseley
|
eddfa0bf6b
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ci: generate XML coverage report for codecov
|
2024-11-29 11:05:47 -07:00 |
|
Fischer Moseley
|
7015be8fe9
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meta: update package name on PyPI
|
2024-11-28 09:40:40 -08:00 |
|
Fischer Moseley
|
1e9e7081ed
|
docs: update package name in installation instructions
|
2024-11-27 21:30:12 -08:00 |
|
Fischer Moseley
|
f43732354d
|
meta: fix coverage path
|
2024-11-27 20:56:20 -08:00 |
|
Fischer Moseley
|
cb7e1e4c2a
|
meta: bump version to 1.1.0 ahead of release
|
2024-11-27 18:17:30 -08:00 |
|
Fischer Moseley
|
56223132c0
|
ci: run pre-commit on all files in CI
|
2024-11-27 19:10:52 -07:00 |