request #325 from Daryl Miles. Made a few simple style changes
to conform to (what is vaguely defined as) the overall programming
style for magic (passed down from John Ousterhout).
Fix code scanning alert no. 52: Multiplication result converted to larger type (#49)
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Fix code scanning alert no. 140: Incorrect return-value check for a 'scanf'-like function (#23)
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Fix code scanning alert no. 138: Incorrect return-value check for a 'scanf'-like function (#22)
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Fix code scanning alert no. 149: Incorrect return-value check for a 'scanf'-like function (#10)
* Create codeql.yml
* Fix code scanning alert no. 149: Incorrect return-value check for a 'scanf'-like function
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depending on the order of extraction devices. Specifically, the
case of a source-drain tied FET was breaking out of a loop when
it should have been breaking out of a double loop.
can provide a delta offset such as "l+0.06", indicating that
the extraction model has a length larger than the drawn device.
Previously the value was assumed to be in microns but did not
scale between the .ext file and the SPICE netlist. Corrected
so that it scales like the other parameter values, being
converted to internal units and tracking the internal grid
scale.
"unexpected asymmetric device" is printed prematurely, as it
is inside a loop checking over all device entries compatible
with a device type. Also: Flagged an issue with the "label"
keyword in the "cifinput" section of a tech file. The "label"
keyword cannot be used in conjunction with boolean operators.
It can only connect labels on a specific GDS type to one magic
type. Unfortunately, because this was not flagged before as
an error or warning, the incorrect usage has crept into a lot
of tech files. This uncovers an underlying issue that labels
must be allowed to automatically reconnect types, which is
undermined by the "no-reconnect-labels" cifinput option. That
issue will be addressed in an upcoming commit.
to be declared for each device model, so that different models can
be specified for different parameter ranges. For example, this
will simplify the definition of the high-sheet-rho poly resistors
and the bipolar transistors in sky130 by removing the need for ID
marker layers; it also allows the correct device model to be
extracted when reading data from GDS that does not contain the
extra (and not foundry-approved) ID markers.
be output twice for scaled devices (such as diodes in the sky130
process). Above and beyond the typo, though, the implementation
of offsets is not very well thought out and needs to be revised.
For one, the +/- notation can be confused with signs in the
parameter expression; that is also fixed in this commit. But
there is currently no way to express both a scale and an offset
for a device parameter.
'+' and '-' in the same way that '*' is currently used for specifying
a parameter scaling. The combination of a scale and offset for the
same parameter has not (yet) been implemented.
from ext2spice due to "equiv" statements in the .ext file. The
algorithm was not properly keeping the port as the preferred
name of the node, resulting in the non-preferred name being
used instead of the port name in the output. This would happen
only if there was a label on a net that had a different name than
the port name. The error became much more prevalent after changing
the extract behavior to make "extract do aliases" default. Also
fixed a somewhat related minor error in which magic would print an
error message about ports being shorted together on the same kind
of net where both a port and a (different) label were attached to
the net. Since the non-port label is not a preferred name, then
there should be no warning message. The warning is only intended
for cases where two (or more) ports are truly shorted together.
perimeter are not initialized, and if a terminal perimeter/area
calculation is missed (which is happening on devices with terminals
in planes other than the plane of the identifying type), then the
perimeter/area of a previously handled device will get output.
(2) Corrected an error with "flatten -inplace" in which the command
fails to deal with instance arrays.
"space" is considered part of the substrate, then the check for
planes to search should exclude "space" from the type mask
first. Otherwise, all planes get searched, not just the substrate.
Also: The same routine can falsely flag a device terminal as
substrate if a split tile is marked as the device's region. This
was also fixed.
partitioning of unshielded areas reaching outward from any given
edge, caused by using a boundary value in the 2nd recursion call
that had been modified for the 1st recursion call and so was no
longer valid.
(truly) missing a terminal (such as a MOSCAP made with a gate
extending into but not crossing a diffusion region). Added the
most requested GUI feature, which is a vertical scrollbar on the
parameterized device window (could be improved by maximizing
window height without exceeding display height).
222 from Sean Cross. Corrected a few places where the blanket
conversion "Region"->"ExtRegion" picked up some comment lines
that were unrelated to the structure name.
the "connected other node to. . ." message when terminals of a
device are shorted. A long enough node name, especially one
created by concatenating hierarchy when flattening a cell, can
easily overrun the short 256-byte string buffer. Fixed by
changing strcat() to strncat().
isolate the terminal areas of a device (e.g., source and drain)
and calculate their area and perimeter individually for the
device (in addition to the traditional method of calculating
area and perimeter of each resistance class for the entire node).
Also: Reworked the SPICE syntax output to generate SI values
in the range 1-1000 with the appropriate suffix (e.g., "20u")
instead of defaulting to "u" for lengths and "p" for areas.
This prevents it from producing weird units like "150000u" when
a process definition already includes a scalefactor.
Reworked the "extresist" code to use the device terminal area
and perimeter. This fixes an error in which "extresist" would
lose these values and "ext2spice" with option "extresist on"
would generate a new netlist output with zero terminal areas
and perimeters.
parameters l1 and l2. Provides a way to pass the source or drain
length as a parameter for, for example, an extended FET drain
implemented as a resistor abutting the FET gate. Could potentially
be used as a way to determine source/drain area and perimeter
without resorting to measurements of a shared node.
use of a resistor type as a FET extended drain, allowing the
FET drain node to short across to the other side of the resistor
so that the resistor is absorbed into the FET device. Used with
the GF180MCU process to describe the salicide-block ESD FET types.
attempt is made to write an abstract view to GDS. This behavior can
be overridded with the new command option "gds abstract [enable|disable]".
Also: Corrected extraction to allow split tiles to be set as the
reference tile for a node. Previously this was allowed only if the
tile was the first to be searched, but that can cause different tiles to
be marked as the reference depending on where the search starts,
resulting in different names for the same node in .ext files, which is
bad. Also: Modified the LEF annotation to avoid bad entries in the LEF
that would create layers in the layout where none exist.
caused by other code that can move the plane of a device to match
the plane of a port. Solved by retaining the original plane of the
node in the extTransRec structure, and using that to determine the
device plane for purposes of calculating perimeters and not double-
counting contacts.
using the newer methods for nearest-edge searching and fringe area
of effect. Removed a same-net check in a routine that removes
capacitances that are redundant due to hierarchical overlaps; these
redundancies must be checked on shapes within the same net. Corrected
(again) an out-of-clip-bounds check.
which instead of defining a device or subcircuit that exists inside
the cell, instead redefines the cell itself as a device or subcircuit
model that exists in the PDK. This is used where a specific layout
subcell has its own associated device definition in the PDK. Instead
of the "device" property value being the line that gets generated for
a device in the subcells .ext file, the property value should be the
word "primitive" optionally followed by any parameters that need to
be passed to the subcircuit call.
Most of this had to do with the incorrect use of the parent's substrate
name in extHierSubstrate(). After the correction, there still remains
an issue that is caused when a labeled isolated substrate region overlaps
an extraction tile boundary. I believe that this particular error has
existed for some time and is not new, so I am committing these changes.
effectively forcing the substrate type (e.g., "pwell") to be defined
as delineating isolated substrate areas only (e.g., pwell in deep nwell
or isosub a.k.a. subcut). It does so by erasing all of the substrate
type out of a cell prior to extraction before redrawing it in the
isolated areas. This avoids issues caused by pwell drawn in separate
unconnected areas of a cell, as these are removed and the area treated
as the default substrate everywhere. Has worked on all layouts tested
so far.
check for abstract views to determine how to handle the substrate
node. Running tests to check if this has any negative impact on
the extraction of abstract views that do not specify substrate
and well types.
traditionally been kept for backwards compatibility. However, the
operation of "ext2spice" and "ext2sim" as separate programs has
become extremely difficult to maintain, and so it has been dropped
in favor of folding both into the program as commands, as was done
a long time ago in the Tcl/Tk version.
time ago by cleaning up excess usage of "equiv" lines in the .ext
file output. The hierarchical extraction code did not distinguish
between node names which were output and those that were not,
requiring a setting "extract do aliases" to force all node aliases
to be output with "equiv" statements. So hierarchical names
might be any alias, whether output or not, and "merge" and "cap"
lines might contain references to nodes that were not output,
causing them to be disconnected nodes. This fix handles the
"extract no aliases" (default) case by flagging node names that
are redundant and not output, and not creating hierarchical names
with them.
node representing the global substrate on cells that are abstract
views. Corrected a typecasting issue in ext2spice.c that throws
a compiler warning. Added another check for a cell being editable
when painting, which is a case that was not covered by the
previous code change to address the same issue.
value 1 after finding a substrate connecting type shielded (by deep
nwell, in the example) from the substrate, thus preventing the
search from processing any remaining substrate types. Solved by
changing the return value to zero to keep the search going.
this limited ports to 16384, which seemed reasonable at the time.
However, the sky130_sram_macro layouts connect power and ground in a
way that when coupled with "extract unique" can generate tens of
thousands of ports and overrun the bit field, showing that automation
can do the unexpected. The solution was to split out the port number
from the label record as its own 32-bit value.
to eliminate all redundant names resulting from redundant labels.
Changed the behavior of "goto" so that it will find local names with
slashes, which are the result of using "flatten". A hierarchical
search is done first, as before, but on failure to find a subcell
component, the local cell is searched for the verbatim name.
statements in the .ext file output to those that mark a port as
equivalent to the node name used elsewhere in the file. This
limits unnecessary output of "equiv" statements that can bog down
ext2spice and other commands that use the .ext file contents.
(since these are interpreted by IRSIM, the only known program to
parse .sim output)---the "ext2sim alias on" option now just moves
such statements from the ".sim" file to a ".al" file. Corrected the
ResSimMerge() routine to reverse the nodes, so that the devices
belonging to the aliased node are added to the original node, instead
of the other way around. This corrects "missing gate" and "missing SD"
errors that occur due to nodes connected through the substrate.
implements a method for handling ports in a subcircuit that have different
port names and indexes but are shorted together. "none" is the default
and backwards-compatible behavior that merges ports together, which will
often cause one of the ports to be optimized out of the netlist. "resistor"
will separate the port names with a 0-ohm ideal resistor. "voltage" will
separate the port names with a 0-volt voltage source. This should work
well for simulation and potentially for LVS, although its impact on LVS
has not been fully investigated.
extracting substrate regions, due to failure to clean up the tagged
tiles after exiting a search due to finding a substrate type that
was not the global substrate.
statement in a .ext file require that all aliases of a node name be
rehashed after a node merge, or else node loops can occur. Also
prevented statements of the form "equiv A A" from being output in
the .ext file, as they are useless.
Darryl L. Miles
Tim Edwards
Sean Cross
Anton Blanchard