one place as ohms and another as milliohms. Changed it to be
milliohms always, except when written as output to the lumped
resistance file or as diagnostic output. The result makes more
sense, but now has the issue that the maximum resistance is always
an over-estimate and may need to account for resistances in
parallel.
determining what does and doesn't get into the R-C extraction
output. Added option "debug" and moved all excess diagnostic
information to be gated by this flag. Corrected an issue in
the standard extraction in which the substrate is always output
with zero lumped resistance, preventing it from being checked
by "extresist" for inclusion or exclusion in the .res.ext output.
Reinstated the computation of minimum resistance transistor but
excluded other devices. Added more sane handling of exceptional
conditions like loops. The result is a more consistent check of
nets in the design. However, I still need to recheck the
"rg_maxres" calculation because it appears to be too low.
(1) An incorrect use of ExtResetTiles() was found in "extresist"
which impacts performance, especially for small nets.
(2) Corrected units for resistance tolerance in extresist, and
handled output printing in fs when delay values get below ps
size.
(3) Added command option "extract do unique notopports" to be the
extraction option equivalent of the standalone command
"extract unique notopports".
(4) Changed the "extresist" default for "mindelay" to 1ps from 0,
in response to the observation that lumped resistance from
"extract" can be an extreme overestimate, and the extracted
time delay from "extesist" calculations should be used as a
better determination of whether a net should be output as a
resistor network or not.
(5) Added documentation for both "extract do unique notopports"
and the change to the "extresist" default values.
that "extresist" selects or rejects networks for resistance
extraction. The "tolerance" value, which nobody (including
myself) seems to understand, is now deprecated, replaced by
a handful of more meaningful options: "threshold" to set a
lumped resistance estimate threshold to determined whether or
not to extract a network; "minres" to specify when to prune
small resistors from the resulting tree network, and "mindelay"
to gate the selection and output on the estimated signal
propagation delay. With these settings, I am much better able
to control the size and complexity of the resulting output.
overhaul was to introduce the concept of a "connection point"
between two cells to the ".ext" file format so that it becomes
possible to do proper hierarchical R-C extraction. Previously
this information was not kept in the .ext file, making it
impossible for "extresist" to know what sub-net of a net connects
up or down the hierarchy. However, additional changes were made
to the extresist code (in the resis/ directory) to add the
handling of connections up and down the hierarchy, and to make
the code a lot clearer and fix ambiguous variable and subroutine
names.
The original version of extresist only worked with 4-terminal FET
devices, and handling of devices with fewer terminals was ignored,
and never properly dealt with. This commit fixes the issues with
devices such as diodes that have fewer terminals.
by old code that still references devices like FETs assuming
four ports. I resolved the crash condition but have not worked
on fixing the code to properly handle a variable number of
terminals per device.
code which are relevant and need to be included. Current state
is that hierarchical extresist "basically works" but entry and
exit points through the hierarchy are not being examined, so
results are currently based on port positions and not actual
connections. Also, proper distribution of coupling caps has not
yet been worked on.
Rebased, fixing merge conflict.
"extresist" command continues to work as before. However, the
method now reads from .ext files instead of .sim files, so
generating ".sim" and ".nodes" files is no longer necessary.
In addition, the core code of "extresist" was put directly into
ExtCell.c so that full R-C extraction can be run using
"extract do resistance" followed by "extract all", without
needing to run "extresist" at all other than to set parameters
(e.g., "extresist tolerance 10").
nodes which are created due to having multiple ports with different
names on the same wire (electrically connected pins). This prevents
"extresist" from double-counting the wire.
created use of 'alloc' local variable to track when an allocation occurred
so exit path logic is more straight forward for compiler/analyser to see
potential optimisations.
connection to a net that has been decomposed into a resistor array
cannot be found. This indicates some fundamental error in the way
extresist works. However, it should not be producing an invalid
and unsimulatable netlist. Instead, it makes an arbitrary connection
from the device terminal to the resistor array and adds an entry in
the output netlist (.res.ext file). This results in a poor
representation of the resistor network to that terminal, but an
otherwise simulatable netlist. A warning is issued to note that an
arbitrary connection has been made. This is most typically a
"garbage in, garbage out" situation in which insufficient information
exists in a layout to inform magic on which direction current is
traveling through a net. However, it should be possible to rewrite
the extresist code so that magic makes somewhat informed decisions
about current paths and produces a halfway decent representation of
the actual net, instead of just giving up on the detailed extraction.
Due to use of strcasecmp() or similar C API.
Maybe HAVE_STRINGS_H is needed ? If so which platforms needs this ?
clang18 default warning cleanup (strict)
The '&' has higher precedence, so the expression of the '&' side receive
extra parentheses.
ResMakeRes.c:671:37: warning: suggest parentheses around '&&' within '||'
ResMakeRes.c:942:32: warning: suggest parentheses around '&&' within '||'
ResSimple.c:201:70: warning: suggest parentheses around '&&' within '||'
ResRex.c:1036:28: warning: suggest parentheses around '&&' within '||'
ResRex.c:1038:50: warning: suggest parentheses around '&&' within '||'
ext2sim.c:1341:47: warning: suggest parentheses around '&&' within '||'
ext2spice.c:172:44: warning: suggest parentheses around '&&' within '||'
ext2spice.c:173:49: warning: suggest parentheses around '&&' within '||'
ext2spice.c:3655:50: warning: suggest parentheses around '&&' within '||'
ext2hier.c:1412:50: warning: suggest parentheses around '&&' within '||'
gcrDebug.c:638:55: warning: suggest parentheses around '&&' within '||'
selEnum.c:323:28: warning: suggest parentheses around '&&' within '||'
GCC14 -Wall cleanup series [-Wparentheses]
PlowRules1.c:439:9: warning: suggest parentheses around assignment used as truth value
PlowTech.c:645:17: warning: suggest parentheses around assignment used as truth value
PlowTech.c:652:17: warning: suggest parentheses around assignment used as truth value
PlowTech.c:1019:17: warning: suggest parentheses around assignment used as truth value
ResReadSim.c:270:13: warning: suggest parentheses around assignment used as truth value
ResReadSim.c:871:9: warning: suggest parentheses around assignment used as truth value
ResRex.c:1840:17: warning: suggest parentheses around assignment used as truth value
getrect.c:72:9: warning: suggest parentheses around assignment used as truth value
getrect.c:79:9: warning: suggest parentheses around assignment used as truth value
getrect.c:86:9: warning: suggest parentheses around assignment used as truth value
getrect.c:93:9: warning: suggest parentheses around assignment used as truth value
hash.c:732:16: warning: suggest parentheses around assignment used as truth value
heap.c:328:17: warning: suggest parentheses around assignment used as truth value
heap.c:344:17: warning: suggest parentheses around assignment used as truth value
netlist.c:323:17: warning: suggest parentheses around assignment used as truth value
niceabort.c:121:9: warning: suggest parentheses around assignment used as truth value
path.c:1102:12: warning: suggest parentheses around assignment used as truth value
pathvisit.c:245:13: warning: suggest parentheses around assignment used as truth value
pathvisit.c:295:17: warning: suggest parentheses around assignment used as truth value
tech.c:656:17: warning: suggest parentheses around assignment used as truth value
ext2spice.c:1591:16: warning: suggest parentheses around assignment used as truth value
ext2spice.c:1622:16: warning: suggest parentheses around assignment used as truth value
ext2spice.c:1813:12: warning: suggest parentheses around assignment used as truth value
ext2spice.c:1862:12: warning: suggest parentheses around assignment used as truth value
ext2spice.c:3808:16: warning: suggest parentheses around assignment used as truth value
CalmaRdio.c:437:9: warning: suggest parentheses around assignment used as truth value
CalmaWrite.c:396:9: warning: suggest parentheses around assignment used as truth value
CalmaWrite.c:1772:29: warning: suggest parentheses around assignment used as truth value
CalmaWriteZ.c:372:9: warning: suggest parentheses around assignment used as truth value
CalmaWriteZ.c:1608:29: warning: suggest parentheses around assignment used as truth value
CIFrdtech.c:209:9: warning: suggest parentheses around assignment used as truth value
CIFrdtech.c:214:9: warning: suggest parentheses around assignment used as truth value
CIFrdtech.c:220:9: warning: suggest parentheses around assignment used as truth value
CIFrdtech.c:226:9: warning: suggest parentheses around assignment used as truth value
CIFrdutils.c:1258:12: warning: suggest parentheses around assignment used as truth value
GCC14 -Wall cleanup series [-Wparentheses]
a transistor's first tile record is a well or substrate type;
normally this is avoided, but if that's the only device terminal
that connects to the node, it will be used. Also changed the
code to not report a failure when space is found under the
device, when space is allowed as a substrate type. Instead it
will print a message that the substrate is not being extracted as
a resistive network. However, note that the correct solution is
to do what the regular "extract" code does, which is to paint the
substrate type in the cell area first, so that there are valid
tile types to use for extracting the substrate network.
missing from a netlist generated by ext2spice with the "extresist"
option enabled. The first had to do with some parts of nets being
given alias names for a net, and the second was caused during
"extresist" and would also result in error messages about devices
missing terminals.
routine that marks resistors in loops to prevent infinite
recursion, but later incorrectly eliminates those resistors.
Also: Changed the "tolerance" command to affect only the R-C
time constant tolerance. Added a "threshold" command option
that limits output of small resistors. This can help reduce
large networks that are otherwise not reducible by the three
methods of reduction (serial, parallel, and delta-wye), but
does affect output values (slightly). This will probably need
to be revisited at some point.
command for use with "extract path"; the cellname was being cleared
after generating the filename with the extract path, but was being
used afterward, so it needed to be reverted back to the original
value, not just free'd. Otherwise "extresist" will fail to produce
any results.
".res.ext" file from "extresist" after using "extract do local" (and
probably with "extract path" as well). Fixed this, and also made
sure that "extresist" writes the ".res.ext" file to the same location
as ".ext" always, so that handling is consistent throughout the
full R-C extraction process, across the use of "extract", "ext2sim",
"extresist", and "ext2spice".
causing the SI suffix not to be the expected one. Adjusted the
bounds where each SI suffix is used to keep output in the range of
0.1 to 100, although the boundary is very subjective. Made a
correction to the extresist code to scan through all device records
for a tile type. However, (1) there are cases being missed, and (2)
this should not be necessary since all device types should be able
to be known exactly from the contents of the .sim file. Needs more
work.
natural sort instead of ASCII-based sorting, so that ports that
are numbered arrays will be indexed properly by count. Also:
Modified the "extresist" handling of substrate to draw the default
substrate type over the entire cell area (less areas of nwell or
other conflicting type). This allows extresist to extract the
entire substrate as a resistive network. The result is ugly and
may warrant some aggressive network simplification, but it should
at least be realistic.
2-terminal devices without complaining. The previous handling
seemed to be technically correct other than spitting out warnings
about missing terminals.
this limited ports to 16384, which seemed reasonable at the time.
However, the sky130_sram_macro layouts connect power and ground in a
way that when coupled with "extract unique" can generate tens of
thousands of ports and overrun the bit field, showing that automation
can do the unexpected. The solution was to split out the port number
from the label record as its own 32-bit value.
messages which was traced to code that changes a drivepoint position
to match a label; the same drivepoint may be part of the record for
the initial position to search on the net, in which case if the
position is changed, then the tile type needs to be changed to match
the new position.
using qsort() instead of its own linked-list-based sorting, which
is horribly inefficient. This change allows power nets (which
tend to be connected to all transistors) to be extracted in a
reasonable amount of time (hours instead of days).
an optional extra argument to the "select" command that can be used
to select labels by glob-style matching; e.g., "select area labels
VSS*" or "select less area labels *_1". This will help in managing
labels after flattening a standard cell design; e.g., by using
"select less area labels */VDD".
specific nets to extract, rather than excluding them. That allows
"extresist" to target specific nets like the power supply or a clock
tree for extraction.
this appears to work correctly but does not yet handle the implicit
substrate (space as substrate) or "virtually" isolated substrate regions
(which need to be removed for full parasitic extraction).
actually an issue and probably never relevant. extresist now works
except for substrate connections and soft connections between substrate
regions. That will require additional coding, not bugfixing, so I'm
committing the last of this set of bugfixes before starting that.
text formatting. Made one critical correction to ResGetDevice() to
pass the device type; otherwise, devices on different planes (e.g.,
MiM caps) with the same coordinate will always return the device on
the lowest plane, leading to incorrect results and an eventual crash
when the device record is free'd twice.
support of devices with terminals on different plances, such as
capacitors, diodes, and bipolar transistors. Output now appears
to give meaningful results for flattened layouts, although
numerous issues remain for hierarchical layouts.
the last commit, unfortunately. Thanks to Matt Guthaus for alerting me
to this. Also updated parts of the extresist code that remove the
dependence on ResConDCS; this is a minor update and should not affect
the operation of extresist. It is preparatory to doing more work to
support additional device types like capacitors, bipolars, and diodes.
code from extflat from type unsigned long to type TileTypeBitMask.
This increases the number of types of each to 256 and tracks the
number of types, so it should be difficult to exceed this amount.
recursive loop and crash magic. Corrected a number of other issues
along the way, especially one where routines in EFantenna and extresist
make use of array EFDevTypes which was only created by ext2sim and
ext2spice, and freed when done. Having run extresist through valgrind,
there are still issues in the code.
commit, mostly relating to the scale of values in the ".nodes" file
produced by ext2sim. Making this file CIF syntax seemed unnecessary,
so I removed the CIF syntax and scaling. "extresist" can now produce
an apparently valid output on a standard cell layout. Even with the
change, the extresist output is still only pseudo-hierarchical, so
this does not preclude the need for eliminating the .sim format file
in favor of the .ext file, but it provides a working intermediate
form.
types and substrate connections. This is an intermediate step to
switching from a sim file format to an ext file format for input,
but resolves the worst issues of having the sim file not recognize
the devices or the substrate nodes. Implemented by using the sim
subcircuit format introduced in IRSIM with the "user subcircuit"
package. Implementation unfinished (work in progress).
R. Timothy Edwards
Darryl L. Miles