Saving work so I can rebase on changes made to the magic extract
code which are relevant and need to be included. Current state is that hierarchical extresist "basically works" but entry and exit points through the hierarchy are not being examined, so results are currently based on port positions and not actual connections. Also, proper distribution of coupling caps has not yet been worked on. Rebased, fixing merge conflict.
This commit is contained in:
R. Timothy Edwards
parent
4dde62b206
commit
727649b308
103
README
103
README
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@ -49,5 +49,104 @@ because it will have to be run independently in any routine that calls
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"ExtCell". This looks like two places, discounting "ExtTech" which
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shouldn't need it: ExtractOneCell() and extExtractStack().
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Start by running tests of how the existing code works given a hierarchical
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layout.
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Done. Now it should be possible to read the .ext file of every parent
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cell of a cell def to find all of the potential points of entry.
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Dealing with those points of entry will be the hard part.
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First, re-run the existing test (non-hierarchical) to make sure that
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moving the point where extResisForDef() is called didn't mess up
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anything. Looks good.
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Next, run a test of how the existing code works given a hierarchical
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layout. Example in ~/devel/magic/extresist_new/hierarchical/. Copying
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layout from chipalooza_projects_2, top level cell sky130_am_ip__ldo_01v8.
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First problem: Not finding the .ext files when reading for extresist.
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But this literally *just* worked fine for the non-hierarchical cell.
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What gives? --- "EFSearchPath" is NULL, this is not what's changed
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by "extract path"? The value is in global variable ExtLocalPath.
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Oh. . . So it *writes* the .res.ext file to the right place but it
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doesn't *read* the .res.ext file from the right place. This also
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means that the non-hierarchical test pulled the wrong .ext file and
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should be done over, although eyeballing it, it looks okay.
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There is a command "extFileOpen" that should be used.
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Fixed, try again.
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This more or less worked.
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Needs to print out the name of the cell being processed.
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Once cell, looks like the level shifter, had "missing terminal
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connection" errors.
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Might be source-drain connected? No, these are perfectly normal
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transistors. . . Why this cell specifically? Happens even if
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only the cell itself is being extracted (no hierarchy).
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Error issued at ResRex.c:1512. layoutDev->rd_terminals has all
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null contents.
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Note that "rd_fet_gate/source/drain/subs" is equivalent to
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"rd_terminals[0/1/2/3]" and either form might be used. The
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rd_terminals[*] form seems to be used only for initialization.
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Looks like ResNewSDDevice() was never run.
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Would have come from walking the device on all four sides;
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ResNewSDDevice would have been called from ResEachTile.
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Break on ResEachTile() for the gate tile in question, which would
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be at 1406, 563. Apparently that never happens?
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5th call to ResProcessTiles().
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Note that "Adding <node name>" only appears sometimes. When it
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is omitted, resisdata->rg_bigdevres is zero. Example, VPWR?
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rg_bigdevres copied from "minRes" in ResProcessNode().
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"Find largest SD device connected to node" seems non-controversial
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and should produce a result for node VPWR.
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Break on ResProcessNode until node->name is "VPWR". Problem happens
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immediately.
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Ah---Caused by ptr->thisDev->resistance = 0.
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This is "linear resistance" from FET line. In .sim files, this is
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found in the devptr record and is relevant.
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Added code to get the value of device width from the .ext file and
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determine the linear resistance according to the tech file values.
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(Except that the open PDKs don't have these values. . . something
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to deal with later.) (Since this seems important, made it default
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to 10k instead of 0.)
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Oddly, these changes made exactly zero difference to the output.
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"minRes" is being set to zero, perhaps for no good reason.
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Now things are worse: "Adding" only shows up once, for VPB,
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and now there's a new error about "VPWR" being an "orphaned node"
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and being connected (arbitrarily) to "VPWR.t1". . .
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Went back to setting minRes to zero for FORCE or DRIVELOC.
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Anyway, this seems to have nothing to do with the missing terminal
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connection and has just been a distraction.
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Example where ResNewSDDevice() is being called correctly:
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tile = pdiff at 686, 439
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tile has clientdata with resDev = L=30, W=168 @656, 439.
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Tile came from a contact point record, cp->cp_tile[0].
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This does not say a whole lot about why a terminal connection
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wasn't found.
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Staring at it for a while, I get it now: These devices are on nets that
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are split into two unconnected parts but labeled the same. So the
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connectivity is tracing from one of the labels, and the other gets
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unprocessed. Probably gets solved by using "extract do unique"?
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Yes, it does!
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Found an error in other code: "extract do unique" turned a font label
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into a regular label, so it got left that way. No, this is something
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else and is in the original cell. Actually, this is a strange error.
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"select area labels" even when applied to the entire cell, does not
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find (or does not display) VGND, LVPWR, VPWR, or VPB font labels.
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All non-font labels and font labels VNB, A, and X are displayed.
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This behavior is not new and I will punt on it. Have no idea what's
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going on, as the graphics routines appear to be working and displaying
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the font label as expected.
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Anyway, with "extract do unique" and "extract do resistance", I can get
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a full R-C extraction netlist from the LDO layout. That leaves a lot
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to be analyzed. . .
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Will need a simpler hierarchical layout example.
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@ -648,8 +648,21 @@ efBuildEquiv(def, nodeName1, nodeName2, resist, isspice)
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return;
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}
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else if (!resist)
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TxError("Warning: Ports \"%s\" and \"%s\" are electrically "
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{
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char *uptr1, *uptr2;
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/* Do not generate an error message if one or both node names
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* is made by "extract unique".
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*/
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if ((uptr1 = strstr(nodeName1, "_uq")) != 0) *uptr1 = '\0';
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if ((uptr2 = strstr(nodeName2, "_uq")) != 0) *uptr2 = '\0';
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if ((uptr1 == NULL && uptr2 == NULL) ||
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strcmp(nodeName1, nodeName2))
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TxError("Warning: Ports \"%s\" and \"%s\" are electrically "
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"shorted.\n", nodeName1, nodeName2);
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if (uptr1) *uptr1 = '_';
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if (uptr2) *uptr2 = '_';
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}
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else
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/* Do not merge the nodes when folding in extresist parasitics */
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return;
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@ -802,14 +802,34 @@ extOutputNodes(nodeList, outFile)
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lastname = ll->ll_label->lab_text;
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}
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/* Don't print a warning unless both labels are
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* really ports.
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* really ports. Also, don't print a warning for
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* names generated by "extract unique" vs. real
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* pin names or another unique name---"extract
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* unique" does not observe where nets pass through
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* subcircuits, so it tends to over-generated
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* unique names, which "ext2spice" will filter out.
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* For a net to be shorted to itself is not an error.
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* NOTE: Potentially the unique name could be removed
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* here and save ext2spice the trouble.
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*/
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if ((portname != NULL) &&
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(ll->ll_attr == LL_PORTATTR) &&
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(strcmp(ll->ll_label->lab_text, portname)))
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TxError("Warning: Ports \"%s\" and \"%s\" are"
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" electrically shorted.\n",
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text, ll->ll_label->lab_text);
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{
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char *uptr1, *uptr2;
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uptr1 = strstr(text, "_uq");
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uptr2 = strstr(ll->ll_label->lab_text, "_uq");
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if (uptr1) *uptr1 = '\0';
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if (uptr2) *uptr2 = '\0';
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if (strcmp(text, ll->ll_label->lab_text))
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{
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TxError("Warning: Ports \"%s\" and \"%s\" are"
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" electrically shorted.\n",
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text, ll->ll_label->lab_text);
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}
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if (uptr1) *uptr1 = '_';
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if (uptr2) *uptr2 = '_';
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}
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if (!isPort && (ll->ll_attr == LL_PORTATTR))
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portname = ll->ll_label->lab_text;
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}
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@ -39,7 +39,6 @@ static char rcsid[] __attribute__ ((unused)) = "$Header: /usr/cvsroot/magic-8.0/
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#include "debug/debug.h"
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#include "extract/extract.h"
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#include "extract/extractInt.h"
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#include "resis/resis.h"
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#include "utils/signals.h"
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#include "utils/stack.h"
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#include "utils/utils.h"
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@ -51,7 +50,6 @@ static char rcsid[] __attribute__ ((unused)) = "$Header: /usr/cvsroot/magic-8.0/
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/* Forward declarations */
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int extOutputUsesFunc();
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FILE *extFileOpen();
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Plane* extCellFile();
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void extHeader();
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@ -97,7 +95,7 @@ ExtCell(def, outName, doLength)
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if (def->cd_flags & CDNOEXTRACT)
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return extPrepSubstrate(def);
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f = extFileOpen(def, outName, "w", &filename);
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f = ExtFileOpen(def, outName, "w", &filename);
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TxPrintf("Extracting %s into %s:\n", def->cd_name, filename);
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@ -116,25 +114,6 @@ ExtCell(def, outName, doLength)
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savePlane = extCellFile(def, f, doLength);
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if (f != NULL) fclose(f);
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/* Integrated extresist --- Run "extresist" on the cell def just
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* extracted and produce an annotation file "<file>.res.ext".
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*/
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if (ExtOptions & EXT_DOEXTRESIST)
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{
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ResisData *resisdata = ResInit();
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UndoDisable();
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ResOptionsFlags |= ResOpt_Signal;
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resisdata->mainDef = def;
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resisdata->savePlanes = (struct saveList *)NULL; /* unused */
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ExtResisForDef(def, resisdata);
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UndoEnable();
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}
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if (extNumErrors > 0 || extNumWarnings > 0)
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{
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TxPrintf("%s:", def->cd_name);
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@ -152,7 +131,7 @@ ExtCell(def, outName, doLength)
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/*
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* ----------------------------------------------------------------------------
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*
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* extFileOpen --
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* ExtFileOpen --
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*
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* Open the .ext file corresponding to a .mag file.
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* If def->cd_file is non-NULL, the .ext file is just def->cd_file with
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@ -170,7 +149,7 @@ ExtCell(def, outName, doLength)
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*/
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FILE *
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extFileOpen(def, file, mode, prealfile)
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ExtFileOpen(def, file, mode, prealfile)
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CellDef *def; /* Cell whose .ext file is to be written */
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char *file; /* If non-NULL, open 'name'.ext; otherwise,
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* derive filename from 'def' as described
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@ -35,6 +35,7 @@ static char rcsid[] __attribute__ ((unused)) = "$Header: /usr/cvsroot/magic-8.0/
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#include "debug/debug.h"
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#include "extract/extract.h"
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#include "extract/extractInt.h"
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#include "resis/resis.h"
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#include "utils/signals.h"
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#include "utils/stack.h"
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#include "utils/utils.h"
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@ -43,9 +44,6 @@ static char rcsid[] __attribute__ ((unused)) = "$Header: /usr/cvsroot/magic-8.0/
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#include "utils/main.h"
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#include "utils/undo.h"
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/* Imports from elsewhere in this module */
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extern FILE *extFileOpen();
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/* ------------------------ Exported variables ------------------------ */
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/*
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@ -83,16 +81,6 @@ typedef struct _linkedDef {
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struct _linkedDef *ld_next;
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} LinkedDef;
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/* Linked list structure to use to store the substrate plane from each */
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/* extracted CellDef so that they can be returned to the original after */
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/* extraction. */
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struct saveList {
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Plane *sl_plane;
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CellDef *sl_def;
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struct saveList *sl_next;
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};
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/* Stack of defs pending extraction */
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Stack *extDefStack;
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@ -606,7 +594,7 @@ extParents(use, doExtract)
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extDefParentFunc(use->cu_def);
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/* Now extract all the cells we just found */
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extExtractStack(extDefStack, doExtract, (CellDef *) NULL);
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extExtractStack(extDefStack, doExtract, (CellDef *)NULL);
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StackFree(extDefStack);
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/* Replace any modified substrate planes in use->cu_def's children */
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@ -688,7 +676,7 @@ ExtParentArea(use, changedArea, doExtract)
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extDefParentAreaFunc(use->cu_def, use->cu_def, (CellUse *) NULL, &area);
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/* Now extract all the cells we just found */
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extExtractStack(extDefStack, doExtract, (CellDef *) NULL);
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extExtractStack(extDefStack, doExtract, (CellDef *)NULL);
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StackFree(extDefStack);
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}
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@ -806,6 +794,23 @@ ExtractOneCell(def, outName, doLength)
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savePlane = ExtCell(def, outName, doLength);
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/* Run full R-C extraction if specified in options */
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if (ExtOptions & EXT_DOEXTRESIST)
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{
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ResisData *resisdata = ResInit();
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UndoDisable();
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ResOptionsFlags |= ResOpt_Signal;
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resisdata->mainDef = def;
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resisdata->savePlanes = (struct saveList *)NULL; /* unused */
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ExtResisForDef(def, resisdata);
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UndoEnable();
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}
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/* Restore all modified substrate planes and modified labels */
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if (savePlane != NULL) ExtRevertSubstrate(def, savePlane);
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@ -945,7 +950,7 @@ extTimestampMisMatch(def)
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doLocal = (ExtLocalPath == NULL) ? FALSE : TRUE;
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extFile = extFileOpen(def, (char *) NULL, "r", (char **) NULL);
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extFile = ExtFileOpen(def, (char *) NULL, "r", (char **) NULL);
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if (extFile == NULL)
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return (TRUE);
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@ -991,10 +996,18 @@ extExtractStack(stack, doExtract, rootDef)
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bool first = TRUE;
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Plane *savePlane;
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CellDef *def;
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LinkedDef *savelist = NULL, *revlist = NULL, *newld;
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struct saveList *newsl, *sl = (struct saveList *)NULL;
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while ((def = (CellDef *) StackPop(stack)))
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{
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if (ExtOptions & EXT_DOEXTRESIST)
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{
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newld = (LinkedDef *)mallocMagic(sizeof(LinkedDef));
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newld->ld_def = def;
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newld->ld_next = savelist;
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savelist = newld;
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}
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def->cd_client = (ClientData) 0;
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if (!SigInterruptPending)
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{
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@ -1027,6 +1040,44 @@ extExtractStack(stack, doExtract, rootDef)
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}
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}
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/* Now that all cells have been processed, run full R-C extraction */
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if (ExtOptions & EXT_DOEXTRESIST)
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{
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ResisData *resisdata = ResInit();
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LinkedDef *srchld, *nextld;
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UndoDisable();
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/* Reverse the linked list from top-down to bottom-up */
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srchld = savelist;
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while (srchld != NULL)
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{
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nextld = srchld->ld_next;
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srchld->ld_next = revlist;
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revlist = srchld;
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srchld = nextld;
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}
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/* Reprocess the list and call "extresist" for each cell def */
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srchld = revlist;
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while (srchld != NULL)
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{
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nextld = srchld->ld_next;
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def = srchld->ld_def;
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ResOptionsFlags |= ResOpt_Signal;
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resisdata->mainDef = def;
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resisdata->savePlanes = (struct saveList *)NULL; /* unused */
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TxPrintf("Processing cell %s for resistance extraction.\n", def->cd_name);
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ExtResisForDef(def, resisdata);
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freeMagic(srchld);
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srchld = nextld;
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}
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UndoEnable();
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}
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/* Replace any modified substrate planes and modified labels */
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free_magic1_t mm1 = freeMagic1_init();
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for (; sl; sl = sl->sl_next)
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@ -113,6 +113,8 @@ extern void ExtDumpCaps();
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extern int extEnumTilePerim(Tile *tpIn, TileType dinfo, const TileTypeBitMask *maskp, int pNum, int (*func)(), ClientData cdata);
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extern Plane *extPrepSubstrate();
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extern FILE *ExtFileOpen(CellDef *def, char *file, char *mode, char **prealfile);
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/* C99 compat */
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extern void ExtAll();
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@ -58,6 +58,7 @@ static char rcsid[] __attribute__ ((unused)) = "$Header: /usr/cvsroot/magic-8.0/
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#define DEV_NAME 2
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#define DEV_X 3
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#define DEV_Y 4
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#define DEV_PARAM_START 7
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#define NODES_NODENAME 1
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#define NODES_NODEX 4
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@ -102,7 +103,7 @@ ResFixPoint *ResFixList;
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*/
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int
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ResReadExt(char *extfile)
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ResReadExt(CellDef *def)
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{
|
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char *line = NULL, *argv[128];
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int result, locresult;
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@ -111,31 +112,12 @@ ResReadExt(char *extfile)
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CellDef *dbdef;
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ResExtNode *curnode;
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/* Search for the .ext fie in the same way that efReadDef() does. */
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fp = PaOpen(extfile, "r", ".ext", EFSearchPath, EFLibPath, (char **)NULL);
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if ((fp == NULL) && ((dbdef = DBCellLookDef(extfile)) != NULL)
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&& (dbdef->cd_file != NULL))
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||||
{
|
||||
char *filepath, *sptr;
|
||||
|
||||
filepath = StrDup((char **)NULL, dbdef->cd_file);
|
||||
sptr = strrchr(filepath, '/');
|
||||
if (sptr)
|
||||
{
|
||||
*sptr = '\0';
|
||||
fp = PaOpen(extfile, "r", ".ext", filepath, EFLibPath, (char **)NULL);
|
||||
}
|
||||
freeMagic(filepath);
|
||||
}
|
||||
|
||||
/* Try with the standard search path */
|
||||
if ((fp == NULL) && (EFSearchPath == NULL))
|
||||
fp = PaOpen(extfile, "r", ".ext", Path, EFLibPath, (char **)NULL);
|
||||
/* Search for the .ext file in the same way that efReadDef() does. */
|
||||
|
||||
fp = ExtFileOpen(def, (char *)NULL, "r", (char **)NULL);
|
||||
if (fp == NULL)
|
||||
{
|
||||
TxError("Cannot open file %s%s\n", extfile, ".ext");
|
||||
TxError("Cannot open file %s%s\n", def->cd_name, ".ext");
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
|
@ -335,11 +317,11 @@ ResReadDevice(int argc,
|
|||
TileType ttype;
|
||||
HashEntry *entry;
|
||||
ResExtNode *node;
|
||||
ResValue rpersquare;
|
||||
float wval;
|
||||
|
||||
device = (RDev *)mallocMagic((unsigned)(sizeof(RDev)));
|
||||
|
||||
device->resistance = 0; /* Linear resistance from FET line, unused */
|
||||
|
||||
device->status = FALSE;
|
||||
device->nextDev = ResRDevList;
|
||||
|
||||
|
|
@ -365,10 +347,25 @@ ResReadDevice(int argc,
|
|||
device->drain = (ResExtNode *)NULL;
|
||||
device->subs = (ResExtNode *)NULL;
|
||||
|
||||
/* Pass over parameters and find the next argument */
|
||||
entry = HashLookOnly(&devptr->exts_deviceResist, "linear");
|
||||
if (entry != NULL)
|
||||
rpersquare = (ResValue)(spointertype)HashGetValue(entry);
|
||||
else
|
||||
rpersquare = (ResValue)10000.0; /* Default to a sane value */
|
||||
|
||||
/* For devices, the device width is in the parameter list */
|
||||
wval = 0.0;
|
||||
for (i = DEV_Y; i < argc; i++)
|
||||
if (!StrIsInt(argv[i]) && !(strchr(argv[i], '=')))
|
||||
{
|
||||
char *eptr;
|
||||
if ((eptr = strchr(argv[i], '=')) != NULL)
|
||||
{
|
||||
if (*argv[i] == 'w')
|
||||
sscanf(eptr + 1, "%f", &wval);
|
||||
}
|
||||
else if (!StrIsInt(argv[i]))
|
||||
break;
|
||||
}
|
||||
|
||||
if (i == argc)
|
||||
{
|
||||
|
|
@ -376,6 +373,8 @@ ResReadDevice(int argc,
|
|||
argv[DEV_NAME]);
|
||||
return 1;
|
||||
}
|
||||
else
|
||||
device->resistance = wval * rpersquare; /* Channel resistance */
|
||||
|
||||
/* Find and record the device terminal nodes */
|
||||
/* Note that this only records up to two terminals matching FET
|
||||
|
|
@ -448,11 +447,11 @@ ResReadFET(int argc,
|
|||
TileType ttype;
|
||||
HashEntry *entry;
|
||||
ResExtNode *node;
|
||||
ResValue rpersquare;
|
||||
float area, perim, wval, lval;
|
||||
|
||||
device = (RDev *)mallocMagic((unsigned)(sizeof(RDev)));
|
||||
|
||||
device->resistance = 0; /* Linear resistance from FET line, unused */
|
||||
|
||||
device->status = FALSE;
|
||||
device->nextDev = ResRDevList;
|
||||
|
||||
|
|
@ -469,11 +468,25 @@ ResReadFET(int argc,
|
|||
device->location.p_x = atoi(argv[FET_X]);
|
||||
device->location.p_y = atoi(argv[FET_Y]);
|
||||
|
||||
device->rs_gattr=RDEV_NOATTR;
|
||||
device->rs_sattr=RDEV_NOATTR;
|
||||
device->rs_dattr=RDEV_NOATTR;
|
||||
device->rs_gattr = RDEV_NOATTR;
|
||||
device->rs_sattr = RDEV_NOATTR;
|
||||
device->rs_dattr = RDEV_NOATTR;
|
||||
device->rs_devptr = devptr;
|
||||
|
||||
entry = HashLookOnly(&devptr->exts_deviceResist, "linear");
|
||||
if (entry != NULL)
|
||||
rpersquare = (ResValue)(spointertype)HashGetValue(entry);
|
||||
else
|
||||
rpersquare = (ResValue)10000.0; /* Default to a sane value */
|
||||
|
||||
/* For old-style FETs, the width is determined from area and perimeter */
|
||||
area = MagAtof(argv[FET_AREA]);
|
||||
perim = MagAtof(argv[FET_PERIM]);
|
||||
lval = 0.5 * (perim + sqrt(perim * perim - 4 * area));
|
||||
wval = area / lval;
|
||||
|
||||
device->resistance = wval * rpersquare; /* Channel resistance */
|
||||
|
||||
/* Find and record the FET terminal nodes */
|
||||
|
||||
entry = HashFind(&ResNodeTable, argv[FET_GATE]);
|
||||
|
|
|
|||
|
|
@ -114,7 +114,7 @@ ExtResisForDef(celldef, resisdata)
|
|||
|
||||
HashInit(&ResNodeTable, INITFLATSIZE, HT_STRINGKEYS);
|
||||
/* Read in the .ext file */
|
||||
result = (ResReadExt(celldef->cd_name) == 0);
|
||||
result = (ResReadExt(celldef) == 0);
|
||||
|
||||
/* Clean up the EFDevTypes table */
|
||||
for (idx = 0; idx < EFDevNumTypes; idx++) freeMagic(EFDevTypes[idx]);
|
||||
|
|
@ -1043,20 +1043,17 @@ ResProcessNode(
|
|||
}
|
||||
}
|
||||
|
||||
/* special handling for FORCE and DRIVELOC labels: */
|
||||
/* set minRes = node->minsizeres if it exists, 0 otherwise */
|
||||
/* Special handling for FORCE and DRIVELOC labels: */
|
||||
/* Set minRes = node->minsizeres if it exists, 0 otherwise. */
|
||||
|
||||
if (node->status & (FORCE|DRIVELOC))
|
||||
{
|
||||
if (node->status & MINSIZE)
|
||||
{
|
||||
minRes = node->minsizeres;
|
||||
}
|
||||
else
|
||||
{
|
||||
minRes = 0;
|
||||
}
|
||||
if (node->status & DRIVELOC)
|
||||
|
||||
if (node->status & DRIVELOC)
|
||||
{
|
||||
resisdata->rg_devloc = &node->drivepoint;
|
||||
resisdata->rg_status |= DRIVEONLY;
|
||||
|
|
@ -1825,6 +1822,9 @@ ResWriteExtFile(celldef, node, resisdata, nidx, eidx)
|
|||
node->name, resisdata->rg_Tdi / Z_TO_P, RCdev / Z_TO_P);
|
||||
}
|
||||
}
|
||||
else
|
||||
TxPrintf("Adding %s\n", node->name);
|
||||
|
||||
for (ptr = node->firstDev; ptr != NULL; ptr=ptr->nextDev)
|
||||
{
|
||||
if ((layoutDev = ResGetDevice(&ptr->thisDev->location, ptr->thisDev->rs_ttype)))
|
||||
|
|
|
|||
Loading…
Reference in New Issue