Matthias Koefferlein
71f646c24f
WIP: updated test data for latest updates, don't sort LVSDB on reading for consistency
2019-07-27 21:42:51 +02:00
Matthias Koefferlein
169cc5246d
WIP: updated golden data for new device sorting in cross reference.
2019-07-27 20:37:41 +02:00
Matthias Koefferlein
b4fa4b1bae
Flattening of layout with circuit flattening.
...
Technically, the layout isn't flattened, but connections are made
which allow regenerating the layout even after the circuit
has been flattened.
2019-07-27 00:37:22 +02:00
Matthias Koefferlein
198b5bb5e4
Updated another golden testdata variant for MSVC
2019-07-24 23:29:13 +02:00
Matthias Koefferlein
45d9261ba9
Updated test golden data variants for MSVC builds
2019-07-24 22:15:15 +02:00
Matthias Koefferlein
64d32c1ae9
LVS tests are more stable because of sorting of terminal names before assigning them (no hash order)
2019-07-24 21:23:19 +02:00
Matthias Koefferlein
afb5cea576
Added "device_scaling" to LVS
...
Plus: added some missing files
Implementation details:
* scaling factor was introduced in DeviceExtractor::extract
* for easy implementation this is available in "sdbu"
* "sdbu" is made available in GSI
* to test this, the db::compare_netlist had to be enhanced to
exactly check device parameters
* enhancement of LVS script framework and doc updates
2019-07-24 00:16:47 +02:00
Matthias Koefferlein
6e6e449eef
Consolidated test data for lvs:full - there are too many variants to support pure text compare. We use the netlist comparer now.
2019-07-21 09:20:44 +02:00
Matthias Koefferlein
c268b7b7c3
Provide golden netlist testdata for LVS test - variant 3
2019-07-19 16:47:57 +02:00
Matthias Köfferlein
b3e9915259
Provide special LVS test golden data for Windows (slight differences in shape order etc.)
2019-07-16 00:40:43 +02:00
Matthias Koefferlein
c7e883cdb2
SPICE reader now assigned net names as pin names.
2019-07-12 19:00:27 +02:00
Matthias Koefferlein
a47190f3ab
Write short versions of LVS and L2N DB by default.
2019-07-12 17:43:43 +02:00
Matthias Koefferlein
e32ee570c7
Alternative algorithm for subcircuit matching - tests updated, refactoring
2019-07-11 23:19:02 +02:00
Matthias Koefferlein
0d9273aaf6
WIP: new subcircuit match algorithm
2019-07-11 00:16:36 +02:00
Matthias Koefferlein
1e3d62ca3a
Provide bulk label for blackboxed cells
2019-07-09 20:23:47 +02:00
Matthias Koefferlein
cef96902ad
Boundary for circuits, reverted automatic generation of global pins
...
- global pins have been generated for device cells too and lead
to implicit pins which may not be desired. The original problem
was how to make abstract circuits comparable. This has to be
solved differently.
- Circuit boundaries are good for displaying the boxes for
abstract circuits
2019-07-09 19:55:48 +02:00
Matthias Koefferlein
bdb8a7bcc2
WIP: reverted modifications on SPICE reader.
2019-07-08 21:51:59 +02:00
Matthias Koefferlein
9625caea65
WIP: added full LVS test.
2019-07-08 21:43:06 +02:00
Matthias Koefferlein
b48453633f
WIP: some fixes and small enhancements. New tests.
2019-07-08 00:09:10 +02:00
Matthias Koefferlein
bc2d9448d6
Providing LVS tests.
2019-07-07 21:33:28 +02:00
Matthias Koefferlein
95a1e38fe3
WIP: better reproducablility for .lvsdb layer names, updated tests.
2019-07-07 19:39:00 +02:00
Matthias Koefferlein
0595ec2e0f
WIP: one more test for LVS
2019-07-06 09:08:32 +02:00
Matthias Koefferlein
2f6aae7204
WIP: refactoring, added first tests for LVS
2019-07-06 08:52:40 +02:00
Matthias Koefferlein
8aa6f4edcf
WIP: added more test data, doc links
2019-07-02 02:03:58 +02:00
Matthias Koefferlein
ae71356052
Added reference circuit
2019-07-02 00:30:50 +02:00
Matthias Koefferlein
5bfed544b7
Added inverter test layout
2019-07-02 00:27:05 +02:00
Matthias Koefferlein
9f26553d4b
Added inverter test layout
2019-07-02 00:25:31 +02:00