iverilog/vhdlpp
Martin Whitaker c59d27e19f Remove more clang warnings.
clang warns that the yyinput function generated by flex is never used.
2011-09-25 10:14:16 -07:00
..
Makefile.in Write package headers to a library file 2011-07-19 19:19:27 -07:00
README.txt Fix some space issues. 2011-09-11 11:41:38 -07:00
architec.cc Delete dynamically allocated objects in vhdlpp 2011-07-28 15:03:28 -07:00
architec.h Use multimap in VHDL Component Instantiations 2011-07-24 10:08:14 -07:00
architec_debug.cc properly handle vhdl open ports in component instantiations. 2011-06-12 16:59:07 -07:00
architec_elaborate.cc Add semantics check in component instantiation 2011-07-24 10:14:41 -07:00
architec_emit.cc Report some missed emit error count. 2011-08-21 16:40:06 -07:00
compiler.cc Add file/line information to entities and ports 2011-01-18 17:03:51 -08:00
compiler.h Add VHDL support for named libraries 2011-07-30 15:04:07 -07:00
debug.cc Handle the basics of aggregate expressions 2011-09-03 17:11:55 -07:00
entity.cc Fix most of the cppcheck warnings in the vhdlpp directory. 2011-07-30 09:35:12 -07:00
entity.h Fix most of the cppcheck warnings in the vhdlpp directory. 2011-07-30 09:35:12 -07:00
entity_elaborate.cc Fix most of the cppcheck warnings in the vhdlpp directory. 2011-07-30 09:35:12 -07:00
entity_emit.cc Report some missed emit error count. 2011-08-21 16:40:06 -07:00
entity_stream.cc Write package headers to a library file 2011-07-19 19:19:27 -07:00
expression.cc Emit code for the to_unsigned() bulit-in function. 2011-09-18 19:31:28 -07:00
expression.h Emit code for the to_unsigned() bulit-in function. 2011-09-18 19:31:28 -07:00
expression_elaborate.cc Evaluate VHDL <name>'length attribute at compile time. 2011-09-18 17:45:06 -07:00
expression_emit.cc Emit code for the to_unsigned() bulit-in function. 2011-09-18 19:31:28 -07:00
ivl_assert.h Distinguish bit selects of entity ports from function calls. 2011-09-11 15:28:58 -07:00
lexor.lex Remove more clang warnings. 2011-09-25 10:14:16 -07:00
lexor_keyword.gperf properly handle vhdl open ports in component instantiations. 2011-06-12 16:59:07 -07:00
library.cc Add VHDL support for named libraries 2011-07-30 15:04:07 -07:00
main.cc Add VHDL support for named libraries 2011-07-30 15:04:07 -07:00
package.cc Merge branch 'master' into work7 2011-07-24 11:06:22 -07:00
package.h Write package headers to a library file 2011-07-19 19:19:27 -07:00
parse.y Emit code for the to_unsigned() bulit-in function. 2011-09-18 19:31:28 -07:00
parse_api.h Add VHDL support for named libraries 2011-07-30 15:04:07 -07:00
parse_misc.cc Distinguish bit selects of entity ports from function calls. 2011-09-11 15:28:58 -07:00
parse_misc.h Distinguish bit selects of entity ports from function calls. 2011-09-11 15:28:58 -07:00
parse_types.h Generate code for vhdl for loops. 2011-09-18 15:51:31 -07:00
parse_wrap.h Parse/decorate sequential statements. 2011-05-08 16:40:35 -07:00
scope.cc Distinguish bit selects of entity ports from function calls. 2011-09-11 15:28:58 -07:00
scope.h Distinguish bit selects of entity ports from function calls. 2011-09-11 15:28:58 -07:00
sequential.cc Generate code for vhdl for loops. 2011-09-18 15:51:31 -07:00
sequential.h Generate code for vhdl for loops. 2011-09-18 15:51:31 -07:00
sequential_debug.cc Handle variables in process statements 2011-08-17 20:19:15 -07:00
sequential_elaborate.cc Generate code for vhdl for loops. 2011-09-18 15:51:31 -07:00
sequential_emit.cc Generate code for vhdl for loops. 2011-09-18 15:51:31 -07:00
vhdlint.cc Remove clang/clang++ warnings. 2011-09-25 10:14:04 -07:00
vhdlint.h Remove clang/clang++ warnings. 2011-09-25 10:14:04 -07:00
vhdlnum.h Introductory changes for numbers handling 2011-02-10 18:34:13 -08:00
vhdlpp_config.h.in Introduce shell of vhdlpp program. 2011-01-18 17:03:51 -08:00
vhdlreal.cc Fix spacing problems. 2011-03-03 11:21:31 -08:00
vhdlreal.h Fix spacing problems. 2011-03-03 11:21:31 -08:00
vsignal.cc Handle variables in process statements 2011-08-17 20:19:15 -07:00
vsignal.h Handle variables in process statements 2011-08-17 20:19:15 -07:00
vtype.cc Add support for constants and package types. 2011-04-17 17:19:09 -07:00
vtype.h Merge branch 'master' into work7 2011-07-24 11:06:22 -07:00
vtype_elaborate.cc Add support for constants and package types. 2011-04-17 17:19:09 -07:00
vtype_emit.cc Emit VHDL symbols as escaped identifiers 2011-08-20 12:11:49 -07:00
vtype_stream.cc Fix most of the cppcheck warnings in the vhdlpp directory. 2011-07-30 09:35:12 -07:00

README.txt

vhdlpp COMMAND LINE FLAGS:

-D <token>
  Debug flags. The token can be:

  * yydebug | no-yydebug

  * entities=<path>

-L <path>
  Library path. Add the directory name to the front of the library
  search path. The library search path is initially empty.

-V
  Display version on stdout

-v
  Verbose: Display version on stderr, and enable verbose messages to
  stderr.

-w <path>
  Work path. This is the directory where the working directory is.


LIBRARY FORMAT:

The vhdlpp program stores libraries as directory that contain
packages. The name of the directory (in lower case) is the name of the
library as used on the "import" statement. Within that library, there
are packages in files named <foo>.pkg. For example:

    <directory>/...
       sample/...
         test1.pkg
	 test2.pkg
       bar/...
         test3.pkg

Use the "+vhdl-libdir+<directory>" record in a config file to tell
Icarus Verilog that <directory> is a place to look for libraries. Then
in your VHDL code, access packages like this:

    library sample;
    library bar;
    use sample.test1.all;
    use bar.test3.all;

The *.pkg files are just VHDL code containing only the package with
the same name. When Icarus Verilog encounters the "use <lib>.<name>.*;"
statement, it looks for the <name>.pkg file in the <lib> library and
parses that file to get the package header declared therin.