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Mono Color

• 09cfbc6240 Core handles subsignal expressions. steve 1999-04-25 00:44:10 +0000
• 32b52cbb97 Make debug output file parameters. steve 1999-04-23 04:34:32 +0000
• d3350c9b27 Add to vvm proceedural memory references. steve 1999-04-22 04:56:58 +0000
• 5895d3c98d Add memories to the parse and elaboration phases. steve 1999-04-19 01:59:36 +0000
• bd40e5dfe1 Support sized decimal numbers, Fix operator precedence order. steve 1999-03-16 04:44:45 +0000
• 51b4f70c8f Add some logical operators. steve 1999-03-16 04:43:46 +0000
• b7f833dd71 Support more operators, especially logical. steve 1999-03-15 02:43:32 +0000
• 5ee3a41d2a Add the AND and OR bitwise operators. steve 1999-03-15 02:42:44 +0000
• 13a6f05463 Prevent the duplicate allocation of ESignal objects. steve 1999-03-01 03:27:53 +0000
• a2bc27318f Handle default case. steve 1999-02-22 03:01:12 +0000
• e2a37a8ccd Add support for module parameters. steve 1999-02-21 17:01:57 +0000
• 9d0a266705 Mangle that handles device instance numbers. steve 1999-02-15 05:52:50 +0000
• 3f4d5bf376 Fix off-by-one placement of hex bytes in a number. steve 1999-02-15 05:52:08 +0000
• e5f5f41515 Elaborate gate ranges. steve 1999-02-15 02:06:15 +0000
• fef81958bc Do not generate code for signals, instead use the NetESignal node to generate gate-like signal devices. steve 1999-02-08 03:55:55 +0000
• 30a3953c85 Turn the NetESignal into a NetNode so that it can connect to the netlist. Implement the case statement. Convince t-vvm to output code for the case statement. steve 1999-02-08 02:49:56 +0000
• 8bdd381cdf Parse and elaborate the Verilog CASE statement. steve 1999-02-03 04:20:11 +0000
• a7ad8985ac Carry some line info to the netlist, Dump line numbers for processes. Elaborate prints errors about port vector width mismatch Emit better handles null statements. steve 1999-02-01 00:26:48 +0000
• 8e73ccf8f8 Ignore ivl. steve 1999-02-01 00:24:43 +0000
• 15ff852487 Missing start methods. steve 1999-01-31 18:15:55 +0000
• fb439c78b9 Add the LineInfo class to carry the source file location of things. PGate, Statement and PProcess. steve 1999-01-25 05:45:56 +0000
• 4b92e91a54 change the program name to ivl. steve 1999-01-25 05:41:56 +0000
• 3d2993be0a Support null target for generating no output. steve 1999-01-24 01:35:08 +0000
• d1e2b036fc Add startup after initialization. steve 1999-01-01 01:46:01 +0000
• a4ce4d97ba Support the start() method. steve 1999-01-01 01:44:56 +0000
• 1e0660522f Proberly print vectors in binary. steve 1999-01-01 01:44:40 +0000
• 63a8b4abe2 Function to calculate wire initial value. steve 1998-12-20 02:05:41 +0000
• 2c1df3e6f7 Parse more UDP input edge descriptions. steve 1998-12-18 05:16:25 +0000
• 4e2c0036aa VVM support for small sequential UDP objects. steve 1998-12-17 23:54:58 +0000
• 10b345bd16 Fully elaborate Sequential UDP behavior. steve 1998-12-14 02:01:34 +0000
• 45f45f73b7 Support the include directive. steve 1998-12-09 04:02:47 +0000
• ed02ae33c7 Fix 2pin logic gates. steve 1998-12-09 02:43:19 +0000
• 9a73433759 Generate OBUF or IBUF attributes (and the gates to garry them) where a wire is a pad. This involved figuring out enough of the netlist to know when such was needed, and to generate new gates and signales to handle what's missing. steve 1998-12-07 04:53:16 +0000
• ada45acb0c Add the nobufz function to eliminate bufz objects, Object links are marked with direction, constant propagation is more careful will wide links, Signal folding is aware of attributes, and the XNF target can dump UDP objects based on LCA attributes. steve 1998-12-02 04:37:13 +0000
• e097c999d5 Elaborate UDP devices, Support UDP type attributes, and pass those attributes to nodes that are instantiated by elaboration, Put modules into a map instead of a simple list. steve 1998-12-01 00:42:13 +0000
• 91aad30e1f Parse UDP primitives all the way to pform. steve 1998-11-25 02:35:53 +0000
• af8d6fbf01 NetAssign handles lvalues as pin links instead of a signal pointer, Wire attributes added, Ability to parse UDP descriptions added, XNF generates EXT records for signals with the PAD attribute. steve 1998-11-23 00:20:22 +0000
• 338240c37b Give anonymous modules a name when elaborated. steve 1998-11-21 19:19:44 +0000
• ac71df5257 Add -f flags for generic flag key/values. steve 1998-11-18 04:25:22 +0000
• 4661006e4b Add the sigfold function that unlinks excess signal nodes, and add the XNF target. steve 1998-11-16 05:03:52 +0000
• 3d6d334f80 Introduce netlist optimizations with the cprop function to do constant propogation. steve 1998-11-13 06:23:17 +0000
• 6b2fa19429 Handle while loops. steve 1998-11-11 03:13:04 +0000
• d27f260bc1 Check net ranges in declarations. steve 1998-11-11 00:01:51 +0000
• 7859de1e4e Add support it vvm target for level-sensitive triggers (i.e. the Verilog wait). Fix display of $time is format strings. steve 1998-11-10 00:48:31 +0000
• 8705aa94c6 Add vvm library. steve 1998-11-09 23:44:10 +0000
• d189165ae9 Oops, forgot return from operator<< steve 1998-11-09 19:03:26 +0000
• ebad845fc3 Add procedural while loops, Parse procedural for loops, Add procedural wait statements, Add constant nodes, Add XNOR logic gate, Make vvm output look a bit prettier. steve 1998-11-09 18:55:33 +0000
• 9a93912ce7 Ignore generated dep directory. steve 1998-11-09 18:50:16 +0000
• 47a444fb92 Calculate expression widths at elaboration time. steve 1998-11-07 19:17:10 +0000
• b118634189 Handle procedural conditional, and some of the conditional expressions. steve 1998-11-07 17:05:05 +0000
• 5836c8aa4b Properly dump 0 length numbers. steve 1998-11-07 17:04:48 +0000
• 43c20f33c8 Make sure dep is a directory. steve 1998-11-07 17:01:36 +0000
• 3fb7a053be Introduce verilog to CVS. steve 1998-11-03 23:28:49 +0000