Introduce netlist optimizations with the
cprop function to do constant propogation.
This commit is contained in:
steve
parent
6b2fa19429
commit
3d6d334f80
2
Makefile
2
Makefile
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@ -8,7 +8,7 @@ CXXFLAGS = -O -g -Wall -Wno-uninitialized
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#TT = t-debug.o t-vvm.o
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TT = t-verilog.o t-vvm.o
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O = main.o design_dump.o elaborate.o emit.o eval.o lexor.o mangle.o \
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O = main.o cprop.o design_dump.o elaborate.o emit.o eval.o lexor.o mangle.o \
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netlist.o parse.o parse_misc.o pform.o pform_dump.o stupid.o verinum.o \
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target.o targets.o Module.o PExpr.o Statement.o $(TT)
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@ -0,0 +1,190 @@
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/*
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* Copyright (c) 1998 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: cprop.cc,v 1.1 1998/11/13 06:23:17 steve Exp $"
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#endif
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# include "netlist.h"
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# include <assert.h>
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/*
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* The cprop function below invokes constant propogation where
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* possible. The elaboration generates NetConst objects. I can remove
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* these and replace the gates connected to it with simpler ones. I
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* may even be able to replace nets with a new constant.
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*/
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static bool is_a_const_node(const NetNode*obj)
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{
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return dynamic_cast<const NetConst*>(obj);
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}
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static bool const_into_xnor(Design*des, NetConst*obj,
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NetLogic*log, unsigned pin)
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{
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assert(pin > 0);
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/* if this is the last input pin of the XNOR device, then
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the device is simply buffering the constant value. */
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if (log->pin_count() == 2) {
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cerr << "cprop: delete gate " << log->name() <<
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" and propogate " << obj->value() << "." << endl;
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assert(pin == 1);
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connect(log->pin(0), log->pin(1));
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delete log;
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return true;
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}
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/* If this is a constant 0, then replace the gate with one
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1-pin smaller. Skip this pin. */
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if (obj->value() == verinum::V0) {
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cerr << "cprop: disconnect pin " << pin << " from gate "
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<< log->name() << "." << endl;
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NetLogic*tmp = new NetLogic(log->name(),
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log->pin_count()-1,
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NetLogic::XNOR);
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connect(log->pin(0), tmp->pin(0));
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unsigned idx, jdx;
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for (idx = 1, jdx = 1 ; idx < log->pin_count() ; idx += 1) {
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if (idx == pin) continue;
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connect(log->pin(idx), tmp->pin(jdx));
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jdx += 1;
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}
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delete log;
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des->add_node(tmp);
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return true;
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}
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/* If this is a constant 1, then replace the gate with an XOR
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that is 1-pin smaller. Removing the constant 1 causes the
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sense of the output to change. */
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if (obj->value() == verinum::V1) {
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cerr << "cprop: disconnect pin " << pin << " from gate "
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<< log->name() << "." << endl;
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NetLogic*tmp = new NetLogic(log->name(),
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log->pin_count()-1,
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NetLogic::XOR);
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connect(log->pin(0), tmp->pin(0));
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unsigned idx, jdx;
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for (idx = 1, jdx = 1 ; idx < log->pin_count() ; idx += 1) {
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if (idx == pin) continue;
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connect(log->pin(idx), tmp->pin(jdx));
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jdx += 1;
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}
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delete log;
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des->add_node(tmp);
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return true;
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}
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/* If this is a constant X or Z, then the gate is certain to
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generate an X. Replace the gate with a constant X. This may
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cause other signals all over to become dangling. */
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if ((obj->value() == verinum::Vx) || (obj->value() == verinum::Vz)) {
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cerr << "cprop: replace gate " << log->name() << " with "
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"a constant X." << endl;
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NetConst*tmp = new NetConst(log->name(), verinum::Vx);
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connect(log->pin(0), tmp->pin(0));
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delete log;
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des->add_node(tmp);
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return true;
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}
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return false;
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}
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static void look_for_core_logic(Design*des, NetConst*obj)
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{
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NetObj*cur = obj;
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unsigned pin = 0;
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for (obj->pin(0).next_link(cur, pin)
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; cur != obj
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; cur->pin(pin).next_link(cur, pin)) {
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NetLogic*log = dynamic_cast<NetLogic*>(cur);
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if (log == 0)
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continue;
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bool flag = false;
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switch (log->type()) {
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case NetLogic::XNOR:
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flag = const_into_xnor(des, obj, log, pin);
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break;
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default:
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break;
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}
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/* If the optimization test tells me that a link was
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deleted, restart the scan. */
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if (flag) obj->pin(0).next_link(cur, pin);
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}
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}
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/*
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* This function looks to see if the constant is connected to nothing
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* but signals. If that is the case, delete the dangling constant and
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* the now useless signals.
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*/
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static void dangling_const(Design*des, NetConst*obj)
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{
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NetObj*cur;
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unsigned pin;
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for (obj->pin(0).next_link(cur, pin)
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; cur != obj
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; cur->pin(pin).next_link(cur, pin)) {
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if (! dynamic_cast<NetNet*>(cur))
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return;
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}
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obj->pin(0).next_link(cur, pin);
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while (cur != obj) {
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cerr << "cprop: delete dangling signal " << cur->name() <<
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"." << endl;
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delete cur;
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obj->pin(0).next_link(cur, pin);
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}
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delete obj;
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}
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void cprop(Design*des)
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{
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des->clear_node_marks();
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while (NetNode*obj = des->find_node(&is_a_const_node)) {
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NetConst*cur = dynamic_cast<NetConst*>(obj);
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look_for_core_logic(des, cur);
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cur->set_mark();
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dangling_const(des, cur);
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}
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}
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/*
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* $Log: cprop.cc,v $
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* Revision 1.1 1998/11/13 06:23:17 steve
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* Introduce netlist optimizations with the
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* cprop function to do constant propogation.
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*
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*/
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52
main.cc
52
main.cc
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@ -17,12 +17,13 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: main.cc,v 1.2 1998/11/07 17:05:05 steve Exp $"
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#ident "$Id: main.cc,v 1.3 1998/11/13 06:23:17 steve Exp $"
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#endif
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# include <stdio.h>
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# include <iostream.h>
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# include <fstream>
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# include <queue>
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# include <unistd.h>
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# include "pform.h"
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# include "netlist.h"
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@ -36,23 +37,52 @@ string start_module = "";
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extern Design* elaborate(const list<Module*>&modules, const string&root);
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extern void emit(ostream&o, const Design*, const char*);
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extern void cprop(Design*des);
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extern void stupid(Design*des);
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typedef void (*net_func)(Design*);
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static struct net_func_map {
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const char*name;
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void (*func)(Design*);
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} func_table[] = {
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{ "stupid", &stupid },
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{ "cprop", &cprop },
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{ 0, 0 }
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};
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net_func name_to_net_func(const string&name)
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{
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for (unsigned idx = 0 ; func_table[idx].name ; idx += 1)
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if (name == func_table[idx].name)
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return func_table[idx].func;
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return 0;
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}
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int main(int argc, char*argv[])
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{
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bool dump_flag = false;
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bool optimize_flag = false;
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const char* out_path = 0;
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int opt;
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unsigned flag_errors = 0;
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queue<net_func> net_func_queue;
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while ((opt = getopt(argc, argv, "DOo:s:t:")) != EOF) switch (opt) {
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while ((opt = getopt(argc, argv, "DF:o:s:t:")) != EOF) switch (opt) {
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case 'D':
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dump_flag = true;
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break;
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case 'O':
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optimize_flag = true;
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break;
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case 'F': {
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net_func tmp = name_to_net_func(optarg);
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if (tmp == 0) {
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cerr << "No such design transform function ``"
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<< optarg << "''." << endl;
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break;
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}
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net_func_queue.push(tmp);
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break;
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}
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case 'o':
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out_path = optarg;
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break;
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@ -114,8 +144,10 @@ int main(int argc, char*argv[])
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return 1;
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}
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if (optimize_flag) {
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stupid(des);
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while (!net_func_queue.empty()) {
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net_func func = net_func_queue.front();
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net_func_queue.pop();
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func(des);
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}
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if (dump_flag) {
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@ -144,6 +176,10 @@ int main(int argc, char*argv[])
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/*
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* $Log: main.cc,v $
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* Revision 1.3 1998/11/13 06:23:17 steve
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* Introduce netlist optimizations with the
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* cprop function to do constant propogation.
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*
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* Revision 1.2 1998/11/07 17:05:05 steve
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* Handle procedural conditional, and some
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* of the conditional expressions.
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49
netlist.cc
49
netlist.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: netlist.cc,v 1.4 1998/11/09 18:55:34 steve Exp $"
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#ident "$Id: netlist.cc,v 1.5 1998/11/13 06:23:17 steve Exp $"
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#endif
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# include <cassert>
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@ -63,7 +63,7 @@ const NetNet* find_link_signal(const NetObj*net, unsigned pin, unsigned&bidx)
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}
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NetObj::NetObj(const string&n, unsigned np)
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: name_(n), npins_(np), delay1_(0), delay2_(0), delay3_(0)
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: name_(n), npins_(np), delay1_(0), delay2_(0), delay3_(0), mark_(false)
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{
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pins_ = new Link[npins_];
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for (unsigned idx = 0 ; idx < npins_ ; idx += 1) {
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@ -265,20 +265,6 @@ NetNet* Design::find_signal(const string&name)
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return 0;
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}
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void Design::scan_signals(SigFunctor*fun)
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{
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if (signals_ == 0)
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return;
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NetNet*cur = signals_->sig_next_;
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do {
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NetNet*next = cur->sig_next_;
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fun->sig_function(cur);
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cur = next;
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} while (cur != signals_->sig_next_);
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}
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void Design::add_node(NetNode*net)
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{
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assert(net->design_ == 0);
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@ -317,9 +303,40 @@ void Design::add_process(NetProcTop*pro)
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procs_ = pro;
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}
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void Design::clear_node_marks()
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{
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if (nodes_ == 0)
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return;
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NetNode*cur = nodes_;
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do {
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cur->set_mark(false);
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cur = cur->node_next_;
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} while (cur != nodes_);
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}
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NetNode* Design::find_node(bool (*func)(const NetNode*))
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{
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if (nodes_ == 0)
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return 0;
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NetNode*cur = nodes_->node_next_;
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do {
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if ((cur->test_mark() == false) && func(cur))
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return cur;
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cur = cur->node_next_;
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} while (cur != nodes_->node_next_);
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return 0;
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}
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/*
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* $Log: netlist.cc,v $
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* Revision 1.5 1998/11/13 06:23:17 steve
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* Introduce netlist optimizations with the
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* cprop function to do constant propogation.
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*
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* Revision 1.4 1998/11/09 18:55:34 steve
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* Add procedural while loops,
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* Parse procedural for loops,
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|
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19
netlist.h
19
netlist.h
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: netlist.h,v 1.4 1998/11/09 18:55:34 steve Exp $"
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#ident "$Id: netlist.h,v 1.5 1998/11/13 06:23:17 steve Exp $"
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#endif
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/*
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@ -117,6 +117,9 @@ class NetObj {
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void delay2(unsigned d) { delay2_ = d; }
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void delay3(unsigned d) { delay3_ = d; }
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bool test_mark() const { return mark_; }
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void set_mark(bool flag=true) { mark_ = flag; }
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Link&pin(unsigned idx) { return pins_[idx]; }
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const Link&pin(unsigned idx) const { return pins_[idx]; }
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@ -130,6 +133,8 @@ class NetObj {
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unsigned delay1_;
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unsigned delay2_;
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unsigned delay3_;
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bool mark_;
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};
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/*
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@ -667,12 +672,8 @@ class Design {
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void dump(ostream&) const;
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void emit(ostream&, struct target_t*) const;
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class SigFunctor {
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public:
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virtual void sig_function(NetNet*) =0;
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};
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void scan_signals(SigFunctor*);
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void clear_node_marks();
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NetNode*find_node(bool (*test)(const NetNode*));
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private:
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// List all the signals in the design.
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@ -709,6 +710,10 @@ inline ostream& operator << (ostream&o, const NetExpr&exp)
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/*
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* $Log: netlist.h,v $
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* Revision 1.5 1998/11/13 06:23:17 steve
|
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* Introduce netlist optimizations with the
|
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* cprop function to do constant propogation.
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*
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* Revision 1.4 1998/11/09 18:55:34 steve
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* Add procedural while loops,
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* Parse procedural for loops,
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|
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51
stupid.cc
51
stupid.cc
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@ -17,63 +17,22 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: stupid.cc,v 1.1 1998/11/03 23:29:05 steve Exp $"
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#ident "$Id: stupid.cc,v 1.2 1998/11/13 06:23:17 steve Exp $"
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#endif
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# include "netlist.h"
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# include <vector>
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vector<NetObj::Link*>* list_link_nodes(NetObj::Link&link)
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{
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NetObj*net;
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unsigned npin;
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vector<NetObj::Link*>*result = new vector<NetObj::Link*>;
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link.cur_link(net, npin);
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NetObj*cur = net;
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unsigned cpin = npin;
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do {
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if (dynamic_cast<NetNode*>(cur))
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result->push_back(&cur->pin(cpin));
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cur->pin(cpin).next_link(cur, cpin);
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} while ((cur != net) || (cpin != npin));
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return result;
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}
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/*
|
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* This function scans a design and removes artifacts from the
|
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* elaboration step, and maybe a few other stupid inefficiencies.
|
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*/
|
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class Functor : public Design::SigFunctor {
|
||||
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||||
public:
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virtual void sig_function(NetNet*);
|
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};
|
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void Functor::sig_function(NetNet*net)
|
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{
|
||||
for (unsigned idx = 0 ; idx < net->pin_count() ; idx += 1) {
|
||||
vector<NetObj::Link*>*nodes = list_link_nodes(net->pin(idx));
|
||||
#if 0
|
||||
cerr << "XXXX " << net->name() << "[" << idx << "] "
|
||||
"nodes->size() == " << nodes->size() << endl;
|
||||
#endif
|
||||
delete nodes;
|
||||
}
|
||||
}
|
||||
|
||||
void stupid(Design*des)
|
||||
{
|
||||
Functor fun;
|
||||
des->scan_signals(&fun);
|
||||
}
|
||||
|
||||
/*
|
||||
* $Log: stupid.cc,v $
|
||||
* Revision 1.2 1998/11/13 06:23:17 steve
|
||||
* Introduce netlist optimizations with the
|
||||
* cprop function to do constant propogation.
|
||||
*
|
||||
* Revision 1.1 1998/11/03 23:29:05 steve
|
||||
* Introduce verilog to CVS.
|
||||
*
|
||||
|
|
|
|||
Loading…
Reference in New Issue