Add -f flags for generic flag key/values.
This commit is contained in:
steve
parent
4661006e4b
commit
ac71df5257
|
|
@ -0,0 +1,89 @@
|
|||
|
||||
INVOKING
|
||||
|
||||
The vl command is the compiler driver, that invokes the parser,
|
||||
optimization functions and the code generator.
|
||||
|
||||
Usage: vl [-s <module>] [-o <file>] [-D] [-F <name>] [-t <name>] file
|
||||
vl -h
|
||||
|
||||
-F <name>
|
||||
Use this flag to request an optimization function be applied
|
||||
to the netlist before it is sent to the target output
|
||||
stage. Any number of -F options may be given, to specify a
|
||||
variety of processing steps. The steps will be applied in
|
||||
order, with the output of one uses as the input to the next.
|
||||
|
||||
The function is specified by name. Use the "vl -h" command to
|
||||
get a list of configured function names.
|
||||
|
||||
-f <assign>
|
||||
Use this flag to set a parameter value. The format of the
|
||||
assignment is <key>=<value> where key is any string up to the
|
||||
first '=', and <value> is the rest of the option. If the '='
|
||||
is omitted, then the key is assigned the empty string.
|
||||
|
||||
The useful keys are defined by the functions and the target in
|
||||
use. These assignments are specifically useful for passing
|
||||
target specific information to the target backend, or
|
||||
options/parameters to optimization functions, if any are defined.
|
||||
|
||||
-o <file>
|
||||
Normally, the generated result is sent to standard
|
||||
output. Use the -o flag to specify an output file for the
|
||||
generated result.
|
||||
|
||||
-s <module>
|
||||
Normally, vl will elaborate the only module in the source
|
||||
file. If there are multiple modules, use this option to select
|
||||
the module to be used as the top-level module.
|
||||
|
||||
-t <name>
|
||||
Select the output format for the compiled result. Use the
|
||||
"vl -h" command to get a list of configured targets.
|
||||
|
||||
|
||||
HOW IT WORKS -- STAGES OF PROCESSING
|
||||
|
||||
* Parse
|
||||
|
||||
The verilog compiler starts by parsing the verilog source file. The
|
||||
output of the parse in a list of Module objects in PFORM. The pform
|
||||
(see pform.h) is mostly a direct reflection of the compilation
|
||||
unit. There may be dangling references, and it is not yet clear which
|
||||
module is the root.
|
||||
|
||||
* Elaboration
|
||||
|
||||
This phase takes the pform and generates a netlist. The driver selects
|
||||
(by user request or lucky guess) the root module to elaborate,
|
||||
resolves references and expands the instantiations to form the design
|
||||
netlist.
|
||||
|
||||
The elaborate() function performs the elaboration.
|
||||
|
||||
* Optimization
|
||||
|
||||
This is actually a collection of processing steps that perform
|
||||
optimizations that do not depend on the target technology. Examples of
|
||||
some useful transformations would be,
|
||||
|
||||
- eliminate null effect circuitry,
|
||||
- combinational reduction
|
||||
- Constant propogation
|
||||
|
||||
The actual functions performed are specified on the command line by
|
||||
the -F flags.
|
||||
|
||||
* Code Generation
|
||||
|
||||
This step takes the design netlist and uses it to drive the code
|
||||
generator. (See target.h.) This may require transforming the
|
||||
design to suit the technology.
|
||||
|
||||
The emit() method of the Design class performs this step. It runs
|
||||
through the design elements, calling target functions as need arises
|
||||
to generate actual output.
|
||||
|
||||
The target code generator to used is given by the -t flag on the
|
||||
command line.
|
||||
34
main.cc
34
main.cc
|
|
@ -17,13 +17,14 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#if !defined(WINNT)
|
||||
#ident "$Id: main.cc,v 1.4 1998/11/16 05:03:52 steve Exp $"
|
||||
#ident "$Id: main.cc,v 1.5 1998/11/18 04:25:22 steve Exp $"
|
||||
#endif
|
||||
|
||||
# include <stdio.h>
|
||||
# include <iostream.h>
|
||||
# include <fstream>
|
||||
# include <queue>
|
||||
# include <map>
|
||||
# include <unistd.h>
|
||||
# include "pform.h"
|
||||
# include "netlist.h"
|
||||
|
|
@ -35,6 +36,25 @@ const char*vl_file = "";
|
|||
const char*target = "verilog";
|
||||
string start_module = "";
|
||||
|
||||
map<string,string> flags;
|
||||
|
||||
static void parm_to_flagmap(const string&flag)
|
||||
{
|
||||
string key, value;
|
||||
unsigned off = flag.find('=');
|
||||
if (off > flag.size()) {
|
||||
key = flag;
|
||||
value = "";
|
||||
|
||||
} else {
|
||||
key = flag.substr(0, off);
|
||||
value = flag.substr(off+1);
|
||||
}
|
||||
|
||||
flags[key] = value;
|
||||
}
|
||||
|
||||
|
||||
extern Design* elaborate(const list<Module*>&modules, const string&root);
|
||||
extern void emit(ostream&o, const Design*, const char*);
|
||||
|
||||
|
|
@ -72,7 +92,7 @@ int main(int argc, char*argv[])
|
|||
unsigned flag_errors = 0;
|
||||
queue<net_func> net_func_queue;
|
||||
|
||||
while ((opt = getopt(argc, argv, "DF:ho:s:t:")) != EOF) switch (opt) {
|
||||
while ((opt = getopt(argc, argv, "DF:f:ho:s:t:")) != EOF) switch (opt) {
|
||||
case 'D':
|
||||
dump_flag = true;
|
||||
break;
|
||||
|
|
@ -81,11 +101,15 @@ int main(int argc, char*argv[])
|
|||
if (tmp == 0) {
|
||||
cerr << "No such design transform function ``"
|
||||
<< optarg << "''." << endl;
|
||||
flag_errors += 1;
|
||||
break;
|
||||
}
|
||||
net_func_queue.push(tmp);
|
||||
break;
|
||||
}
|
||||
case 'f':
|
||||
parm_to_flagmap(optarg);
|
||||
break;
|
||||
case 'h':
|
||||
help_flag = true;
|
||||
break;
|
||||
|
|
@ -160,6 +184,9 @@ int main(int argc, char*argv[])
|
|||
return 1;
|
||||
}
|
||||
|
||||
des->set_flags(flags);
|
||||
|
||||
|
||||
while (!net_func_queue.empty()) {
|
||||
net_func func = net_func_queue.front();
|
||||
net_func_queue.pop();
|
||||
|
|
@ -192,6 +219,9 @@ int main(int argc, char*argv[])
|
|||
|
||||
/*
|
||||
* $Log: main.cc,v $
|
||||
* Revision 1.5 1998/11/18 04:25:22 steve
|
||||
* Add -f flags for generic flag key/values.
|
||||
*
|
||||
* Revision 1.4 1998/11/16 05:03:52 steve
|
||||
* Add the sigfold function that unlinks excess
|
||||
* signal nodes, and add the XNF target.
|
||||
|
|
|
|||
14
netlist.cc
14
netlist.cc
|
|
@ -17,7 +17,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#if !defined(WINNT)
|
||||
#ident "$Id: netlist.cc,v 1.6 1998/11/16 05:03:53 steve Exp $"
|
||||
#ident "$Id: netlist.cc,v 1.7 1998/11/18 04:25:22 steve Exp $"
|
||||
#endif
|
||||
|
||||
# include <cassert>
|
||||
|
|
@ -218,6 +218,15 @@ void NetEUnary::set_width(unsigned w)
|
|||
expr_width(w);
|
||||
}
|
||||
|
||||
string Design::get_flag(const string&key) const
|
||||
{
|
||||
map<string,string>::const_iterator tmp = flags_.find(key);
|
||||
if (tmp == flags_.end())
|
||||
return "";
|
||||
else
|
||||
return (*tmp).second;
|
||||
}
|
||||
|
||||
void Design::add_signal(NetNet*net)
|
||||
{
|
||||
assert(net->design_ == 0);
|
||||
|
|
@ -361,6 +370,9 @@ NetNet* Design::find_signal(bool (*func)(const NetNet*))
|
|||
|
||||
/*
|
||||
* $Log: netlist.cc,v $
|
||||
* Revision 1.7 1998/11/18 04:25:22 steve
|
||||
* Add -f flags for generic flag key/values.
|
||||
*
|
||||
* Revision 1.6 1998/11/16 05:03:53 steve
|
||||
* Add the sigfold function that unlinks excess
|
||||
* signal nodes, and add the XNF target.
|
||||
|
|
|
|||
19
netlist.h
19
netlist.h
|
|
@ -19,7 +19,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#if !defined(WINNT)
|
||||
#ident "$Id: netlist.h,v 1.6 1998/11/16 05:03:53 steve Exp $"
|
||||
#ident "$Id: netlist.h,v 1.7 1998/11/18 04:25:22 steve Exp $"
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
@ -29,6 +29,7 @@
|
|||
* processors.
|
||||
*/
|
||||
# include <string>
|
||||
# include <map>
|
||||
# include "verinum.h"
|
||||
|
||||
class NetNode;
|
||||
|
|
@ -654,6 +655,17 @@ class Design {
|
|||
public:
|
||||
Design() : signals_(0), nodes_(0), procs_(0) { }
|
||||
|
||||
/* The flags are a generic way of accepting command line
|
||||
parameters/flags and passing them to the processing steps
|
||||
that deal with the design. The compilation driver sets the
|
||||
entire flags map after elaboration is done. Subsequent
|
||||
steps can then use the get_flag() function to get the value
|
||||
of an interesting key. */
|
||||
|
||||
void set_flags(const map<string,string>&f) { flags_ = f; }
|
||||
|
||||
string get_flag(const string&key) const;
|
||||
|
||||
|
||||
// SIGNALS
|
||||
|
||||
|
|
@ -688,6 +700,8 @@ class Design {
|
|||
// List the processes in the design.
|
||||
NetProcTop*procs_;
|
||||
|
||||
map<string,string> flags_;
|
||||
|
||||
private: // not implemented
|
||||
Design(const Design&);
|
||||
Design& operator= (const Design&);
|
||||
|
|
@ -713,6 +727,9 @@ inline ostream& operator << (ostream&o, const NetExpr&exp)
|
|||
|
||||
/*
|
||||
* $Log: netlist.h,v $
|
||||
* Revision 1.7 1998/11/18 04:25:22 steve
|
||||
* Add -f flags for generic flag key/values.
|
||||
*
|
||||
* Revision 1.6 1998/11/16 05:03:53 steve
|
||||
* Add the sigfold function that unlinks excess
|
||||
* signal nodes, and add the XNF target.
|
||||
|
|
|
|||
23
t-xnf.cc
23
t-xnf.cc
|
|
@ -17,9 +17,23 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#if !defined(WINNT)
|
||||
#ident "$Id: t-xnf.cc,v 1.1 1998/11/16 05:03:53 steve Exp $"
|
||||
#ident "$Id: t-xnf.cc,v 1.2 1998/11/18 04:25:22 steve Exp $"
|
||||
#endif
|
||||
|
||||
/* XNF BACKEND
|
||||
* This target supports generating Xilinx Netlist Format netlists for
|
||||
* use by Xilinx tools, and other tools that accepts Xilinx designs.
|
||||
*
|
||||
* FLAGS
|
||||
* The XNF backend uses the following flags from the command line to
|
||||
* affect the generated file:
|
||||
*
|
||||
* part=<foo>
|
||||
* Specify the part type. The part string is written into the
|
||||
* PART record. Valid types are defined by Xilinx or the
|
||||
* receiving tools
|
||||
*/
|
||||
|
||||
# include "netlist.h"
|
||||
# include "target.h"
|
||||
|
||||
|
|
@ -55,11 +69,11 @@ string target_xnf::mangle(const string&name)
|
|||
}
|
||||
|
||||
|
||||
void target_xnf::start_design(ostream&os, const Design*)
|
||||
void target_xnf::start_design(ostream&os, const Design*des)
|
||||
{
|
||||
os << "LCANET,6" << endl;
|
||||
os << "PROG,verilog,0.0,\"Steve's Verilog\"" << endl;
|
||||
os << "PART,4000-10" << endl;
|
||||
os << "PART," << des->get_flag("part") << endl;
|
||||
}
|
||||
|
||||
void target_xnf::end_design(ostream&os, const Design*)
|
||||
|
|
@ -124,6 +138,9 @@ extern const struct target tgt_xnf = { "xnf", &target_xnf_obj };
|
|||
|
||||
/*
|
||||
* $Log: t-xnf.cc,v $
|
||||
* Revision 1.2 1998/11/18 04:25:22 steve
|
||||
* Add -f flags for generic flag key/values.
|
||||
*
|
||||
* Revision 1.1 1998/11/16 05:03:53 steve
|
||||
* Add the sigfold function that unlinks excess
|
||||
* signal nodes, and add the XNF target.
|
||||
|
|
|
|||
Loading…
Reference in New Issue