Do not generate code for signals,
instead use the NetESignal node to generate gate-like signal devices.
This commit is contained in:
steve
parent
30a3953c85
commit
fef81958bc
138
t-vvm.cc
138
t-vvm.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: t-vvm.cc,v 1.10 1999/02/08 02:49:56 steve Exp $"
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#ident "$Id: t-vvm.cc,v 1.11 1999/02/08 03:55:55 steve Exp $"
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#endif
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# include <iostream>
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@ -67,8 +67,6 @@ class target_vvm : public target_t {
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ostrstream start_code;
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unsigned process_counter;
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unsigned thread_step_;
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unsigned indent_;
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};
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@ -131,7 +129,7 @@ void vvm_proc_rval::expr_ident(const NetEIdent*expr)
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void vvm_proc_rval::expr_signal(const NetESignal*expr)
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{
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result = mangle(expr->name());
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result = mangle(expr->name()) + "_bits";
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}
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void vvm_proc_rval::expr_unary(const NetEUnary*expr)
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@ -243,9 +241,9 @@ void vvm_parm_rval::expr_signal(const NetESignal*expr)
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string res = make_temp();
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os_ << " vvm_calltf_parm::SIG " << res << ";" << endl;
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os_ << " " << res << ".bits = &" <<
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mangle(expr->name()) << ";" << endl;
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mangle(expr->name()) << "_bits;" << endl;
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os_ << " " << res << ".mon = &" <<
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mangle(expr->name()) << "_mon;" << endl;
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mangle(expr->name()) << ";" << endl;
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result = res;
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}
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@ -298,10 +296,6 @@ void target_vvm::end_design(ostream&os, const Design*mod)
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void target_vvm::signal(ostream&os, const NetNet*sig)
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{
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os << "static vvm_bitset_t<" << sig->pin_count() << "> " <<
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mangle(sig->name()) << "; /* " << sig->name() << " */" << endl;
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os << "static vvm_monitor_t " << mangle(sig->name()) << "_mon(\""
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<< sig->name() << "\");" << endl;
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/* Scan the signals of the vector, passing the initial value
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to the inputs of all the connected devices. */
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@ -341,15 +335,11 @@ void target_vvm::emit_gate_outputfun_(const NetNode*gate)
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unsigned pin;
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gate->pin(0).next_link(cur, pin);
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while (cur != gate) {
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// Skip signals
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if (const NetNet*sig = dynamic_cast<const NetNet*>(cur)) {
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delayed << " " << mangle(sig->name()) << "[" <<
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pin << "] = val;" << endl;
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delayed << " " << mangle(sig->name()) <<
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"_mon.trigger(sim);" << endl;
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if (dynamic_cast<const NetNet*>(cur)) {
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// Skip signals
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} else {
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delayed << " " << mangle(cur->name()) << ".set(sim, "
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<< pin << ", val);" << endl;
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}
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@ -522,8 +512,14 @@ void target_vvm::net_const(ostream&os, const NetConst*gate)
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emit_gate_outputfun_(gate);
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}
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void target_vvm::net_esignal(ostream&, const NetESignal*)
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void target_vvm::net_esignal(ostream&os, const NetESignal*net)
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{
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os << "static vvm_bitset_t<" << net->pin_count() << "> " <<
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mangle(net->name()) << "_bits; /* " << net->name() <<
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" */" << endl;
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os << "static vvm_signal_t<" << net->pin_count() << "> " <<
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mangle(net->name()) << "(\"" << net->name() << "\", &" <<
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mangle(net->name()) << "_bits);" << endl;
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}
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/*
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@ -545,7 +541,6 @@ void target_vvm::net_pevent(ostream&os, const NetPEvent*gate)
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void target_vvm::start_process(ostream&os, const NetProcTop*proc)
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{
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process_counter += 1;
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indent_ = 8;
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thread_step_ = 0;
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os << "class thread" << process_counter <<
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@ -573,7 +568,7 @@ void target_vvm::start_process(ostream&os, const NetProcTop*proc)
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*/
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void target_vvm::proc_assign(ostream&os, const NetAssign*net)
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{
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string rval = emit_proc_rval(os, indent_, net->rval());
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string rval = emit_proc_rval(os, 8, net->rval());
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const NetNet*lval;
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unsigned msb, lsb;
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@ -583,17 +578,10 @@ void target_vvm::proc_assign(ostream&os, const NetAssign*net)
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os << " // " << lval->name() << " = ";
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net->rval()->dump(os);
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os << endl;
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os << " " << mangle(lval->name())
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<< " = " << rval << ";" << endl;
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} else {
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assert(0);
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}
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os << " " << mangle(lval->name()) <<
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"_mon.trigger(sim_);" << endl;
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/* Not only is the lvalue signal assigned to, send the bits to
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all the other pins that are connected to this signal. */
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@ -608,23 +596,14 @@ void target_vvm::proc_assign(ostream&os, const NetAssign*net)
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if (dynamic_cast<const NetAssign*>(cur))
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continue;
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// Skip NetESignal nodes. They are handled as
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// expressions.
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if (dynamic_cast<const NetESignal*>(cur))
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// Skip signals, I'll hit them when I handle the
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// NetESignal nodes.
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if (dynamic_cast<const NetNet*>(cur))
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continue;
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if (const NetNet*sig = dynamic_cast<const NetNet*>(cur)) {
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os << " " << mangle(sig->name())
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<< "[" << pin << "] = " << rval << "[" << idx
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<< "];" << endl;
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os << " " << mangle(sig->name())
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<< "_mon.trigger(sim_);" << endl;
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} else {
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os << " " << mangle(cur->name()) <<
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".set(sim_, " << pin << ", " <<
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rval << "[" << idx << "]);" << endl;
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}
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os << " " << mangle(cur->name()) <<
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".set(sim_, " << pin << ", " <<
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rval << "[" << idx << "]);" << endl;
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}
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}
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}
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@ -651,7 +630,7 @@ void target_vvm::proc_block(ostream&os, const NetBlock*net)
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*/
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void target_vvm::proc_case(ostream&os, const NetCase*net)
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{
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string expr = emit_proc_rval(os, indent_, net->expr());
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string expr = emit_proc_rval(os, 8, net->expr());
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ostrstream sc;
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unsigned default_step_ = thread_step_ + 1;
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@ -662,7 +641,7 @@ void target_vvm::proc_case(ostream&os, const NetCase*net)
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to. Once that is done, return true so that statement is
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executed. */
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for (unsigned idx = 0 ; idx < net->nitems() ; idx += 1) {
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string guard = emit_proc_rval(os, indent_, net->expr(idx));
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string guard = emit_proc_rval(os, 8, net->expr(idx));
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thread_step_ += 1;
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@ -671,16 +650,12 @@ void target_vvm::proc_case(ostream&os, const NetCase*net)
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os << " step_ = &step_" <<
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thread_step_ << "_;" << endl;
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{ unsigned save_indent = indent_;
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indent_ = 8;
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sc << " bool step_" << thread_step_ << "_()" << endl;
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sc << " {" << endl;
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net->stat(idx)->emit_proc(sc, this);
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sc << " step_ = &step_" << default_step_ << "_;" << endl;
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sc << " return true;" << endl;
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sc << " }" << endl;
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indent_ = save_indent;
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}
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sc << " bool step_" << thread_step_ << "_()" << endl;
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sc << " {" << endl;
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net->stat(idx)->emit_proc(sc, this);
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sc << " step_ = &step_" << default_step_ << "_;" << endl;
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sc << " return true;" << endl;
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sc << " }" << endl;
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}
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os << " else" << endl;
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@ -694,11 +669,11 @@ void target_vvm::proc_case(ostream&os, const NetCase*net)
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void target_vvm::proc_condit(ostream&os, const NetCondit*net)
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{
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string expr = emit_proc_rval(os, indent_, net->expr());
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string expr = emit_proc_rval(os, 8, net->expr());
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unsigned if_step = ++thread_step_;
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unsigned if_step = ++thread_step_;
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unsigned else_step = ++thread_step_;
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unsigned out_step = ++thread_step_;
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unsigned out_step = ++thread_step_;
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os << " if (" << expr << "[0] == V1)" << endl;
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os << " step_ = &step_" << if_step << "_;" << endl;
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@ -746,17 +721,11 @@ void target_vvm::proc_task(ostream&os, const NetTask*net)
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void target_vvm::proc_while(ostream&os, const NetWhile*net)
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{
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unsigned ind = indent_;
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indent_ += 4;
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os << setw(ind) << "" << "for (;;) {" << endl;
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string expr = emit_proc_rval(os, indent_, net->expr());
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os << setw(indent_) << "" << "if (" << expr << "[0] != V1)"
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" break;" << endl;
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os << " for (;;) {" << endl;
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string expr = emit_proc_rval(os, 12, net->expr());
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os << " if (" << expr << "[0] != V1) break;" << endl;
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net->emit_proc_recurse(os, this);
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os << setw(ind) << "" << "}" << endl;
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indent_ = ind;
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os << " }" << endl;
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}
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/*
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@ -766,8 +735,7 @@ void target_vvm::proc_while(ostream&os, const NetWhile*net)
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void target_vvm::proc_event(ostream&os, const NetPEvent*proc)
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{
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thread_step_ += 1;
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os << setw(indent_) << "" << "step_ = &step_" << thread_step_ <<
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"_;" << endl;
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os << " step_ = &step_" << thread_step_ << "_;" << endl;
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/* POSITIVE is for the wait construct, and needs to be handled
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specially. The structure of the generated code is:
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@ -790,18 +758,17 @@ void target_vvm::proc_event(ostream&os, const NetPEvent*proc)
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edge. */
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if (proc->edge() == NetPEvent::POSITIVE) {
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os << setw(indent_) << "" << "if (" <<
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mangle(proc->name()) << ".get()==V1) {" << endl;
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os << setw(indent_+3) << "" << "return true;" << endl;
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os << setw(indent_) << "" << "} else {" << endl;
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os << setw(indent_+3) << "" << mangle(proc->name()) <<
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os << " if (" << mangle(proc->name()) <<
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".get()==V1) {" << endl;
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os << " return true;" << endl;
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os << " } else {" << endl;
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os << " " << mangle(proc->name()) <<
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".wait(vvm_pevent::POSEDGE, this);" << endl;
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os << setw(indent_+3) << "" << "return false;" << endl;
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os << setw(indent_) << "" << "}" << endl;
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os << " return false;" << endl;
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os << " }" << endl;
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} else {
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os << setw(indent_) << "" << mangle(proc->name()) <<
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".wait(vvm_pevent::";
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os << " " << mangle(proc->name()) << ".wait(vvm_pevent::";
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switch (proc->edge()) {
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case NetPEvent::ANYEDGE:
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os << "ANYEDGE";
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@ -815,7 +782,7 @@ void target_vvm::proc_event(ostream&os, const NetPEvent*proc)
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break;
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}
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os << ", this);" << endl;
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os << setw(indent_+3) << "" << "return false;" << endl;
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os << " return false;" << endl;
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}
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os << " }" << endl;
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os << " bool step_" << thread_step_ << "_()" << endl;
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@ -844,11 +811,11 @@ void target_vvm::proc_delay(ostream&os, const NetPDelay*proc)
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void target_vvm::end_process(ostream&os, const NetProcTop*proc)
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{
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if (proc->type() == NetProcTop::KALWAYS) {
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os << setw(indent_) << "" << "step_ = &step_0_;" << endl;
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os << setw(indent_) << "" << "return true;" << endl;
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os << " step_ = &step_0_;" << endl;
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os << " return true;" << endl;
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} else {
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os << setw(indent_) << "" << "step_ = 0;" << endl;
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os << setw(indent_) << "" << "return false;" << endl;
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os << " step_ = 0;" << endl;
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os << " return false;" << endl;
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}
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os << " }" << endl;
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@ -864,6 +831,11 @@ extern const struct target tgt_vvm = {
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};
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/*
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* $Log: t-vvm.cc,v $
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* Revision 1.11 1999/02/08 03:55:55 steve
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* Do not generate code for signals,
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* instead use the NetESignal node to
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* generate gate-like signal devices.
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*
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* Revision 1.10 1999/02/08 02:49:56 steve
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* Turn the NetESignal into a NetNode so
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* that it can connect to the netlist.
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31
vvm/vvm.h
31
vvm/vvm.h
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@ -19,11 +19,12 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: vvm.h,v 1.3 1998/12/17 23:54:58 steve Exp $"
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#ident "$Id: vvm.h,v 1.4 1999/02/08 03:55:55 steve Exp $"
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#endif
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# include <vector>
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# include <string>
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# include <cassert>
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/*
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* The Verilog Virtual Machine are definitions for the virtual machine
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@ -101,6 +102,13 @@ template <unsigned WIDTH> class vvm_bitset_t : public vvm_bits_t {
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unsigned get_width() const { return WIDTH; }
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vvm_bit_t get_bit(unsigned idx) const { return bits_[idx]; }
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bool eequal(const vvm_bitset_t<WIDTH>&that) const
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{ for (unsigned idx = 0 ; idx < WIDTH ; idx += 1)
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if (bits_[idx] != that.bits_[idx])
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return false;
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return true;
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}
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private:
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vvm_bit_t bits_[WIDTH];
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};
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@ -215,8 +223,29 @@ class vvm_monitor_t {
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};
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template <unsigned WIDTH> class vvm_signal_t : public vvm_monitor_t {
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public:
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vvm_signal_t(const string&n, vvm_bitset_t<WIDTH>*b)
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: vvm_monitor_t(n), bits_(b)
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{ }
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void set(vvm_simulation*sim, unsigned idx, vvm_bit_t val)
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{ (*bits_)[idx] = val;
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trigger(sim);
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}
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private:
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vvm_bitset_t<WIDTH>*bits_;
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};
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/*
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* $Log: vvm.h,v $
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* Revision 1.4 1999/02/08 03:55:55 steve
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* Do not generate code for signals,
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* instead use the NetESignal node to
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* generate gate-like signal devices.
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*
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* Revision 1.3 1998/12/17 23:54:58 steve
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* VVM support for small sequential UDP objects.
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*
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