Add support it vvm target for level-sensitive
triggers (i.e. the Verilog wait). Fix display of $time is format strings.
This commit is contained in:
steve
parent
8705aa94c6
commit
7859de1e4e
89
t-vvm.cc
89
t-vvm.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: t-vvm.cc,v 1.4 1998/11/09 18:55:34 steve Exp $"
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#ident "$Id: t-vvm.cc,v 1.5 1998/11/10 00:48:31 steve Exp $"
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#endif
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# include <iostream>
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@ -445,12 +445,12 @@ void target_vvm::start_process(ostream&os, const NetProcTop*proc)
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os << " { }" << endl;
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os << " ~thread" << process_counter << "_t() { }" << endl;
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os << endl;
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os << " void go() { (this->*step_)(); }" << endl;
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os << " bool go() { return (this->*step_)(); }" << endl;
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os << " private:" << endl;
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os << " void (thread" << process_counter <<
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os << " bool (thread" << process_counter <<
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"_t::*step_)();" << endl;
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os << " void step_0_() {" << endl;
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os << " bool step_0_() {" << endl;
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}
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/*
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@ -566,25 +566,57 @@ void target_vvm::proc_event(ostream&os, const NetPEvent*proc)
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thread_step_ += 1;
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os << setw(indent_) << "" << "step_ = &step_" << thread_step_ <<
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"_;" << endl;
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os << setw(indent_) << "" << mangle(proc->name()) <<
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".wait(vvm_pevent::";
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switch (proc->edge()) {
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case NetPEvent::ANYEDGE:
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os << "ANYEDGE";
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break;
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case NetPEvent::POSEDGE:
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os << "POSEDGE";
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break;
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case NetPEvent::NEGEDGE:
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os << "NEGEDGE";
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break;
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case NetPEvent::POSITIVE:
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os << "POSITIVE";
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break;
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/* POSITIVE is for the wait construct, and needs to be handled
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specially. The structure of the generated code is:
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if (event.get()==V1) {
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return true;
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} else {
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event.wait(vvm_pevent::POSEDGE, this);
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return false;
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}
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This causes the wait to not even block the thread if the
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event value is already positive, otherwise wait for a
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rising edge. All the edge triggers look like this:
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event.wait(vvm_pevent::POSEDGE, this);
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return false;
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POSEDGE is replaced with the correct type for the desired
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edge. */
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if (proc->edge() == NetPEvent::POSITIVE) {
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os << setw(indent_) << "" << "if (" <<
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mangle(proc->name()) << ".get()==V1) {" << endl;
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os << setw(indent_+3) << "" << "return true;" << endl;
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os << setw(indent_) << "" << "} else {" << endl;
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os << setw(indent_+3) << "" << mangle(proc->name()) <<
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".wait(vvm_pevent::POSEDGE, this);" << endl;
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os << setw(indent_+3) << "" << "return false;" << endl;
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os << setw(indent_) << "" << "}" << endl;
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} else {
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os << setw(indent_) << "" << mangle(proc->name()) <<
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".wait(vvm_pevent::";
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switch (proc->edge()) {
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case NetPEvent::ANYEDGE:
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os << "ANYEDGE";
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break;
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case NetPEvent::POSITIVE:
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case NetPEvent::POSEDGE:
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os << "POSEDGE";
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break;
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case NetPEvent::NEGEDGE:
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os << "NEGEDGE";
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break;
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}
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os << ", this);" << endl;
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os << setw(indent_+3) << "" << "return false;" << endl;
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}
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os << ", this);" << endl;
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os << " }" << endl;
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os << " void step_" << thread_step_ << "_()" << endl;
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os << " bool step_" << thread_step_ << "_()" << endl;
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os << " {" << endl;
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proc->emit_proc_recurse(os, this);
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@ -599,8 +631,9 @@ void target_vvm::proc_delay(ostream&os, const NetPDelay*proc)
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os << " step_ = &step_" << thread_step_ << "_;" << endl;
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os << " sim_->thread_delay(" << proc->delay() << ", this);"
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<< endl;
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os << " return false;" << endl;
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os << " }" << endl;
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os << " void step_" << thread_step_ << "_()" << endl;
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os << " bool step_" << thread_step_ << "_()" << endl;
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os << " {" << endl;
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proc->emit_proc_recurse(os, this);
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@ -609,10 +642,11 @@ void target_vvm::proc_delay(ostream&os, const NetPDelay*proc)
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void target_vvm::end_process(ostream&os, const NetProcTop*proc)
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{
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if (proc->type() == NetProcTop::KALWAYS) {
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os << " step_ = &step_0_;" << endl;
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os << " step_0_(); // XXXX" << endl;
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os << setw(indent_) << "" << "step_ = &step_0_;" << endl;
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os << setw(indent_) << "" << "return true;" << endl;
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} else {
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os << " step_ = 0;" << endl;
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os << setw(indent_) << "" << "step_ = 0;" << endl;
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os << setw(indent_) << "" << "return false;" << endl;
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}
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os << " }" << endl;
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@ -628,6 +662,11 @@ extern const struct target tgt_vvm = {
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};
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/*
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* $Log: t-vvm.cc,v $
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* Revision 1.5 1998/11/10 00:48:31 steve
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* Add support it vvm target for level-sensitive
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* triggers (i.e. the Verilog wait).
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* Fix display of $time is format strings.
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*
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* Revision 1.4 1998/11/09 18:55:34 steve
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* Add procedural while loops,
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* Parse procedural for loops,
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: display.cc,v 1.1 1998/11/09 23:44:10 steve Exp $"
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#ident "$Id: display.cc,v 1.2 1998/11/10 00:48:31 steve Exp $"
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#endif
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# include "vvm.h"
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@ -28,31 +28,35 @@ static void format_bit(ostream&os, class vvm_calltf_parm*parm)
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{
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switch (parm->type()) {
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case vvm_calltf_parm::NONE:
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cout << "z";
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os << "z";
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break;
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case vvm_calltf_parm::ULONG:
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cout << ((parm->as_ulong()&1) ? "0" : "1");
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os << ((parm->as_ulong()&1) ? "0" : "1");
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break;
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case vvm_calltf_parm::STRING:
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cout << parm->as_string();
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os << parm->as_string();
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break;
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case vvm_calltf_parm::BITS:
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cout << parm->as_bits()->get_bit(0);
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os << parm->as_bits()->get_bit(0);
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break;
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}
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}
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static void format_dec(ostream&os, class vvm_calltf_parm*parm)
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static void format_dec(vvm_simulation*sim, ostream&os,
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class vvm_calltf_parm*parm)
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{
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switch (parm->type()) {
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case vvm_calltf_parm::TIME:
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os << sim->get_sim_time();
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break;
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case vvm_calltf_parm::NONE:
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cout << "0";
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os << "0";
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break;
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case vvm_calltf_parm::ULONG:
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cout << parm->as_ulong();
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os << parm->as_ulong();
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break;
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case vvm_calltf_parm::STRING:
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cout << parm->as_string();
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os << parm->as_string();
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break;
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case vvm_calltf_parm::BITS: {
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unsigned long val = 0;
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@ -62,7 +66,7 @@ static void format_dec(ostream&os, class vvm_calltf_parm*parm)
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if (bstr->get_bit(idx) == V1) val |= mask;
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mask <<= 1;
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}
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cout << val;
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os << val;
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break;
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}
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}
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@ -71,6 +75,9 @@ static void format_dec(ostream&os, class vvm_calltf_parm*parm)
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static void format_name(ostream&os, class vvm_calltf_parm*parm)
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{
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switch (parm->type()) {
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case vvm_calltf_parm::TIME:
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os << "$time";
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break;
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case vvm_calltf_parm::NONE:
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break;
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case vvm_calltf_parm::ULONG:
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@ -85,7 +92,8 @@ static void format_name(ostream&os, class vvm_calltf_parm*parm)
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}
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}
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static unsigned format(const string&str, unsigned nparms,
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static unsigned format(vvm_simulation*sim, const string&str,
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unsigned nparms,
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class vvm_calltf_parm*parms)
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{
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char prev = 0;
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@ -101,7 +109,7 @@ static unsigned format(const string&str, unsigned nparms,
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break;
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case 'd':
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case 'D':
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format_dec(cout, parms+next_parm);
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format_dec(sim, cout, parms+next_parm);
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next_parm += 1;
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break;
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case 'm':
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@ -144,8 +152,8 @@ void Sdisplay(vvm_simulation*sim, const string&name,
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cout << parms[idx].as_ulong();
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break;
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case vvm_calltf_parm::STRING:
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idx += format(parms[idx].as_string(),
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nparms-idx-1, parms+idx+1);
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idx += format(sim, parms[idx].as_string(),
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nparms-idx-1, parms+idx+1);
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break;
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case vvm_calltf_parm::BITS:
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cout << *parms[idx].as_bits();
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@ -198,6 +206,11 @@ void Smonitor(vvm_simulation*sim, const string&name,
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/*
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* $Log: display.cc,v $
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* Revision 1.2 1998/11/10 00:48:31 steve
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* Add support it vvm target for level-sensitive
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* triggers (i.e. the Verilog wait).
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* Fix display of $time is format strings.
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*
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* Revision 1.1 1998/11/09 23:44:10 steve
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* Add vvm library.
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*
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: vvm.h,v 1.1 1998/11/09 23:44:10 steve Exp $"
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#ident "$Id: vvm.h,v 1.2 1998/11/10 00:48:31 steve Exp $"
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#endif
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# include <vector>
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@ -81,6 +81,7 @@ class vvm_bits_t {
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virtual vvm_bit_t get_bit(unsigned idx) const =0;
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};
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extern ostream& operator << (ostream&os, vvm_bit_t);
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extern ostream& operator << (ostream&os, const vvm_bits_t&str);
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/*
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@ -214,6 +215,11 @@ class vvm_monitor_t {
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/*
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* $Log: vvm.h,v $
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* Revision 1.2 1998/11/10 00:48:31 steve
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* Add support it vvm target for level-sensitive
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* triggers (i.e. the Verilog wait).
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* Fix display of $time is format strings.
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*
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* Revision 1.1 1998/11/09 23:44:10 steve
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* Add vvm library.
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*
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@ -17,29 +17,35 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: vvm_bit.cc,v 1.1 1998/11/09 23:44:10 steve Exp $"
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#ident "$Id: vvm_bit.cc,v 1.2 1998/11/10 00:48:31 steve Exp $"
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#endif
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# include "vvm.h"
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ostream& operator << (ostream&os, vvm_bit_t bit)
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{
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switch (bit) {
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case V0:
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os << "0";
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break;
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case V1:
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os << "1";
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break;
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case Vx:
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os << "x";
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break;
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case Vz:
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os << "z";
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break;
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}
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return os;
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}
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ostream& operator << (ostream&os, const vvm_bits_t&str)
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{
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os << str.get_width() << "b'";
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for (unsigned idx = str.get_width() ; idx > 0 ; idx -= 1)
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switch (str.get_bit(idx)) {
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case V0:
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os << "0";
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break;
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case V1:
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os << "1";
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break;
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case Vx:
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os << "x";
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break;
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case Vz:
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os << "z";
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break;
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}
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os << str.get_bit(idx);
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return os;
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}
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@ -94,6 +100,11 @@ vvm_bit_t add_with_carry(vvm_bit_t l, vvm_bit_t r, vvm_bit_t&carry)
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/*
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* $Log: vvm_bit.cc,v $
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* Revision 1.2 1998/11/10 00:48:31 steve
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* Add support it vvm target for level-sensitive
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* triggers (i.e. the Verilog wait).
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* Fix display of $time is format strings.
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*
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* Revision 1.1 1998/11/09 23:44:10 steve
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* Add vvm library.
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*
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: vvm_gates.h,v 1.1 1998/11/09 23:44:11 steve Exp $"
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#ident "$Id: vvm_gates.h,v 1.2 1998/11/10 00:48:31 steve Exp $"
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#endif
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# include "vvm.h"
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@ -205,6 +205,7 @@ class vvm_pevent {
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void wait(EDGE, vvm_thread*);
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void set(vvm_simulation*sim, unsigned, vvm_bit_t val);
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vvm_bit_t get() const { return value_; }
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private:
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vvm_bit_t value_;
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@ -218,6 +219,11 @@ class vvm_pevent {
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/*
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* $Log: vvm_gates.h,v $
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* Revision 1.2 1998/11/10 00:48:31 steve
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* Add support it vvm target for level-sensitive
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* triggers (i.e. the Verilog wait).
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* Fix display of $time is format strings.
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*
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* Revision 1.1 1998/11/09 23:44:11 steve
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* Add vvm library.
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*
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: vvm_simulation.cc,v 1.1 1998/11/09 23:44:11 steve Exp $"
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#ident "$Id: vvm_simulation.cc,v 1.2 1998/11/10 00:48:31 steve Exp $"
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#endif
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# include "vvm.h"
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@ -184,7 +184,7 @@ class delay_event : public vvm_event {
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public:
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delay_event(vvm_thread*thr) : thr_(thr) { }
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void event_function() { thr_->go(); }
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void event_function() { while (thr_->go()) /* empty */; }
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private:
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vvm_thread*thr_;
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};
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@ -210,6 +210,11 @@ void vvm_simulation::thread_active(vvm_thread*thr)
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/*
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* $Log: vvm_simulation.cc,v $
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* Revision 1.2 1998/11/10 00:48:31 steve
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* Add support it vvm target for level-sensitive
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* triggers (i.e. the Verilog wait).
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* Fix display of $time is format strings.
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*
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* Revision 1.1 1998/11/09 23:44:11 steve
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* Add vvm library.
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*
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: vvm_thread.h,v 1.1 1998/11/09 23:44:11 steve Exp $"
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#ident "$Id: vvm_thread.h,v 1.2 1998/11/10 00:48:31 steve Exp $"
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#endif
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# include "vvm.h"
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@ -38,7 +38,11 @@ class vvm_thread {
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public:
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explicit vvm_thread(vvm_simulation*sim);
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virtual ~vvm_thread();
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virtual void go() =0;
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// This method executes a setp of the thread. The engine will
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// continue to call go as long as it returns true. The thread
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// will return false if it is ready to give up the CPU.
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virtual bool go() =0;
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protected:
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vvm_simulation*const sim_;
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||||
|
|
@ -46,6 +50,11 @@ class vvm_thread {
|
|||
|
||||
/*
|
||||
* $Log: vvm_thread.h,v $
|
||||
* Revision 1.2 1998/11/10 00:48:31 steve
|
||||
* Add support it vvm target for level-sensitive
|
||||
* triggers (i.e. the Verilog wait).
|
||||
* Fix display of $time is format strings.
|
||||
*
|
||||
* Revision 1.1 1998/11/09 23:44:11 steve
|
||||
* Add vvm library.
|
||||
*
|
||||
|
|
|
|||
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Reference in New Issue