luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
7,046 Commits 23 Branches 234 Tags 41 MiB
Commit Graph

217 Commits

Author SHA1 Message Date
Martin Whitaker 9e25884f12 Fix for br942 - allow function declaration in VHDL architecture. 2013-12-11 23:00:58 +00:00
Cary R 07cc18284c Fix print token/argument mismatches and other cppcheck fixes 2013-09-09 13:34:38 -07:00
Cary R 21b24c7725 Fix more compile warnings and a minor bug 2013-07-11 19:10:25 -07:00
Cary R 3e75f8e41f Remove a compile warning 2013-07-11 18:03:00 -07:00
Stephen Williams ca9616dc7b Better simple_expression parse rules. 2013-06-12 14:21:36 -07:00
Stephen Williams 24bd630cb2 Parse (to sorry messages) unbounded array definitions. 2013-06-12 14:21:36 -07:00
Stephen Williams 8487cb5616 Do a better job of figuring the vtype of an expression. 2013-06-12 14:21:36 -07:00
Stephen Williams d630e4dfe9 Elaborate VHDL entity port types/expressions. 
We need to elaborate expressions so that function calls in
expressions (i.e. ranges) get bound to their proper scope.
This binding is in turn used to emit package scopes. This
is particularly interesting for ports of entities.
 2013-06-12 14:21:35 -07:00
Stephen Williams 3d5765949e Some shorthand type marks in write_to_stream. 2013-06-12 14:21:35 -07:00
Stephen Williams 0fcd2d9db6 Handle rising_edge and falling_edge functions. 2013-06-12 14:21:35 -07:00
Stephen Williams bc77a19059 Use $ivl_unsigned to implement VHDL to_unsigned function. 
The VHDL to_unsigned function with to arguments is best handled
in the ivl elaborator, so have it generate an $ivlh_to_unsigned
function call in the vhdlpp code, and implement it in the ivl
core.

Also, implement the 'length attribute as a $bits() call for
similar reasons.
 2013-06-12 14:09:08 -07:00
Stephen Williams dca6171f5f SV emit function ports in package subprograms. 2013-06-12 14:09:07 -07:00
Stephen Williams 164b5f9348 Fix SV emit of ForLoopStatement and ReturnStmt. 2013-06-12 14:09:07 -07:00
Stephen Williams e927960121 Implement subprogram bodies in package bodies. 2013-06-12 14:09:07 -07:00
Stephen Williams 6394a4d78d Rework scope types and constants so we can tell imported from local names. 
The package emit of types and constants needs to know which names are
from the current type and which are imported from libraries. Rework
the scope handling of those names so that the information is preserved.
 2013-06-12 14:09:07 -07:00
Stephen Williams 13be45bd73 Fix dump of primitive CHARACTER types. 2013-06-12 14:09:07 -07:00
Stephen Williams 7f7decde03 Basic structure for emitting packages. 2013-06-12 14:09:07 -07:00
Stephen Williams d9fea802da Function declarations in packages 
This is still basic. Definitions are still not done.
 2013-06-12 14:09:07 -07:00
Stephen Williams 11682fc7eb Harmless cleanup of comments / initialization warnings. 2013-04-18 18:18:40 -07:00
Cary R d2928d500d Remove a few more compile error messages from RHEL5 2013-04-17 17:46:05 -07:00
Cary R 15379f1750 Remove some compile warnings 2013-04-17 17:13:22 -07:00
Stephen Williams bad8ed39c1 Parse VHDL subprogram bodies and return statements. 2012-11-03 09:54:07 -07:00
Stephen Williams 5651e6e001 Improve error handling. 2012-11-02 19:30:12 -07:00
Stephen Williams c14134aa2e Handle genvar variables in expressions. 
In generate for blocks, there is a genvar that can be used in
expressions within the generate block. Generate this genvar in
the generated output, matched to the generate scope.
 2012-09-07 15:14:48 -07:00
Stephen Williams 85e000ed0c Handle prefix expressions that include array index expressions. 2012-09-03 16:00:10 -07:00
Stephen Williams 7fad717a1e Redesign selected_name rule to better handle complex prefixes 
Prefixes of hierarchical names are complex and cannot be handled
by simple strings, to the rules must be reworked.
 2012-09-03 16:00:10 -07:00
Arun Persaud f5aafc32f9 updated FSF-address 2012-08-29 10:12:10 -07:00
Cary R 4313fbbf1f Fix space errors in various files 2012-08-16 11:13:32 -07:00
Cary R 1749d10966 Fix some clang/bison compile warnings. 2012-08-06 15:49:11 -07:00
Larry Doolittle befff82655 Spelling fixes 
Comments and debug messages.
 2012-07-27 18:25:32 -07:00
Stephen Williams 621c09105c Sort the typedef emits so that types are emitted in the order used. 
It is common for typedefs of complex types to use further typedefs.
Emit the type definitions depth first so that the types that are used
are defined first. This reduces the need for pre-declaration of types.
 2012-05-22 17:31:27 -07:00
Stephen Williams 369a0b9eca VHDL named types work in more places. 2012-05-22 17:31:27 -07:00
Stephen Williams 4748f0cb5e Handle incomplete type declarations 
Use these in the package library to allow for arbitrary mixing
of type declaration and use. This makes writing libraries much
easier.
 2012-05-22 17:31:27 -07:00
Stephen Williams 039e6014fe Rework VType::emit_def methods / use packed arrays to implement arrays. 
VHDL arrays are more like SV packed arrays, so use packed arrays
to implement them.
 2012-05-22 17:31:26 -07:00
Stephen Williams 63b7fe059d Reword concat to handle aggregate arguments. 
When concatenation expressions have aggregate arguments, we need to
get the type of the result down to the aggregate expressions so that
it can know how to interpret the elements.
 2012-05-22 17:31:26 -07:00
Stephen Williams 67af96fee7 Module output ports use data_type_or_implicit 
This cleans up the parsing of module output ports, allows for more
complex types on the ports, and fixes some bugs.
 2012-05-22 17:31:26 -07:00
Stephen Williams 7e202bb5ca Fix emit of struct ports/declarations. 2012-05-22 17:31:26 -07:00
Stephen Williams 71d2401221 Handle VHDL records. 
Elaborate records and emit them as packed SV records. Also handle
record members so handle name prefixes.

While we are at it, handle some cases of array aggregate expressions.
 2012-05-22 17:31:26 -07:00
Stephen Williams ae06863db1 Elaborate prefix names which may be structure variables. 2012-05-22 17:31:26 -07:00
Stephen Williams a5458828cd Some vhdl parser error handling. 2012-05-22 17:31:26 -07:00
Stephen Williams 021d944a30 Probe type of ExpName with a record prefix. 2012-05-22 17:31:25 -07:00
Stephen Williams 7eb89c5548 Parse name prefix syntax for record member reference. 
When signals/variables are records, they are often referenced by
their members, using a prefix.name syntax. Parse that syntax and
generate "sorry" messages in elaboration.
 2012-05-22 17:31:25 -07:00
Stephen Williams 5e7f61ea42 VHDL process sensitivities go to the end of each iteration 2012-05-22 17:31:25 -07:00
Stephen Williams 9b816f6478 Add support for nested when/else expressions. 2012-05-22 17:31:25 -07:00
Stephen Williams 1249b5dd32 Initial support for if_generate syntax. 2012-05-22 17:31:25 -07:00
Stephen Williams 0775e36a67 Properly elaborate argument types for binary relation expressions. 
The argument types of binary relation expressions are decoupled
from the return type for the expression itself.
 2012-05-22 17:31:25 -07:00
Stephen Williams ed3da959f3 Support types in packages. 
Types declared in packages should be written into the package library.
 2012-05-22 17:31:25 -07:00
Stephen Williams 79435924f2 Move some VType::show methods to ::write_to_stream methods. 2012-05-22 17:31:25 -07:00
Stephen Williams 9ed56a6354 Parse record types, and some new aggregate types. 2012-05-22 17:31:25 -07:00
Larry Doolittle 84f14dbc81 Spelling fixes to vhdlpp tree 
Mostly comments as usual, but one error message is changed.
 2012-05-17 16:42:03 -07:00