dc1c3a4043
Fix for GitHub issue #94 - enhance support for SystemVerilog size casting.
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Allow the size expression to be any constant expression. Also ensure that
the expression width and type are correctly calculated and applied.
2016-03-25 21:49:28 +00:00
b5324c7ba2
Fix reference to undefined value (valgrind)
2016-03-24 23:43:07 -07:00
fb77cc4000
Fix a cppcheck warning
2016-03-24 20:23:47 -07:00
9538c81d34
Add check for explicit lifetime when initialising static variables.
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If a static variable declared in a task, function, or block has an
initialisation expression, SystemVerilog requires the declaration to
have an explicit static lifetime. This is supposed to be a compile
error, but for now just output a warning.
Implementing this required adding support in the parser for explicit
lifetimes in variable declarations. For now, just output an error if
the user asks for a lifetime that isn't the default for that scope.
2016-03-19 20:44:36 +00:00
6e718c2e0c
Added support for default subroutine lifetimes (SystemVerilog).
2016-03-19 17:27:27 +00:00
7c3cee5f7a
Updated comment in tgt-vlog95 to reflect changes in variable initialization.
2016-03-19 14:47:38 +00:00
0dcb46e4c4
Fix shadow warning.
2016-03-19 14:42:34 +00:00
72bb63cf42
Variable initialization blocks should be unamed.
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Also add file/line info to initial process.
2016-03-19 14:21:10 +00:00
54feb89bf5
For SystemVerilog, run variable initialization before main simulation starts.
2016-03-19 13:46:09 +00:00
635adfc01e
Fully support variable initialization in tasks/functions/named blocks.
2016-03-19 13:04:38 +00:00
28b446ca30
Use correct type when printing supply pull message
2016-03-15 03:49:20 -07:00
78a49eacef
Merge branch 'master' of github.com:steveicarus/iverilog
2016-03-14 12:26:12 -07:00
1784488096
Spelling and whitespace
2016-03-14 12:25:50 -07:00
dbaf2471f2
Fix for br1001 - connect undriven wand/wor to 'bz in tgt-vvp.
2016-03-13 16:38:55 +00:00
a5dac08a50
tgt-vlog95: Find the original signal when a port connection is cast.
2016-03-12 23:22:14 +00:00
c4b3f256af
Don't mislabel signals as ports when casting port connections.
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The original signal should retain the port type. Moving it to the cast
signal was confusing the vlog95 and stub targets.
2016-03-12 23:17:54 +00:00
081f5e6960
tgt-vlog95: Fix infinite loop caused by searching the wrong scope.
2016-03-12 23:11:11 +00:00
5d9a196819
tgt-vlog95: Handle variable initialisation in named blocks.
2016-03-12 23:06:54 +00:00
dc189fec8c
Added new vvp latch statement to README file.
2016-03-12 12:14:03 +00:00
9d487c6951
vhdlpp: Fixed a few shadow warnings.
2016-03-12 12:03:17 +00:00
708a7d0621
Move some redundant initialisation of bitmasks in synthesis.
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These are made obsolete by an earlier bugfix.
2016-03-12 12:02:22 +00:00
b4d438ea9f
Fixed bug in vlog95 dff output when using asynchronous set.
2016-03-12 11:39:32 +00:00
22bc798696
Added warning when a latch enable is a synthesised expression.
2016-03-12 11:21:23 +00:00
c0542af6bf
Updated copyright dates following previous patch.
2016-03-12 09:10:58 +00:00
89333fa3a5
add latch primitive for vlog95
2016-03-12 09:06:42 +00:00
99afea6946
Added support for LPM latches to vvp.
2016-03-12 09:04:51 +00:00
b47482880c
Added support for LPM latches to stub target.
2016-03-12 09:03:42 +00:00
5dfc9fdefb
Code and comment cleanup for latches in target interface.
2016-03-12 00:10:47 +00:00
d7736d7eba
latch for vvp output
2016-03-11 23:44:06 +00:00
35a61b4680
Add LATCH to target interface
2016-03-11 23:43:58 +00:00
0e537c5465
Enable latch generation in synthesis.
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(reworked patch supplied by Johann Klammer)
2016-03-11 23:29:58 +00:00
81d3b7a25c
Updated copyright notices.
2016-03-11 23:14:55 +00:00
c92b630728
NetLatch class
2016-03-11 23:11:54 +00:00
f176106c54
Added notes on synthesis implementation.
2016-03-11 18:35:13 +00:00
c1c4d8c863
Fix bitmask merging in synthesis.
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A conditional clause that doesn't drive any bits of a particular nexus
should not affect the bitmask generated for that nexus. The completely
undriven case is handled by the enable signal.
2016-03-11 17:32:12 +00:00
6a8303bdaf
Merge pull request #92 from orsonmmz/vhdlpp_fixes
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Vhdlpp fixes
2016-03-07 09:05:36 -08:00
de775975e8
ivl: Fixed slice base calculation
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when range is rising (e.g. logic [0:3] arr) or when it
starts with a non-zero integer (e.g. logic [4:1] arr).
2016-03-07 17:11:53 +01:00
770906ba0d
vhdlpp: Write binary constants as a string of bits.
2016-03-07 17:11:53 +01:00
c25be111a3
vhdlpp: Apply case equality operator for logic type.
2016-03-07 17:11:53 +01:00
41a45a8db0
vhdlpp: Avoid unnecessary toupper() call.
2016-03-07 17:11:53 +01:00
7c10de918e
vhdlpp: read() takes into account the size of the destination variable.
2016-03-07 17:11:53 +01:00
94f7504372
vhdlpp: Subprograms are linked to Package instead of generic Scope.
2016-03-07 17:11:53 +01:00
78d6ee26dd
vhdlpp: Do not allow 'wire real' nets.
2016-03-07 17:11:49 +01:00
7bb4cef9bc
vhdlpp: ExpScopedName class to handle names with a specified scope.
2016-03-07 11:38:11 +01:00
03e85850e1
vhdlpp: Variables are moved to respective process scopes.
2016-03-07 11:38:11 +01:00
b037d533f9
vhdlpp: ProcessStatement inherits after ScopeBase.
2016-03-07 11:38:11 +01:00
25cd0827ba
vhdlpp: Removed ProcessStatement::rewrite_as_always_edge_() & extract_anyedge_().
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Processes sensitive to edges are now handled with $ivlh_{rising,falling}_edge().
2016-03-07 11:38:11 +01:00
7cbb275ffe
vhdlpp: Handle limited-length strings in reports.
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Currently limited-length strings (e.g. string(1 to 4)) are
emulated using 2D array of bits (e.g. bit [1:4][7:0]).
Because of that, ivl treats them as standard vectors and
$display() does not show them as strings. Now, they are
wrapped with $sformatf("%s", ..) to fix it.
2016-03-07 11:38:11 +01:00
e4bc404e99
vhdlpp: ExprVisitor stores the recursion level.
2016-03-07 09:54:28 +01:00
cef45ff21a
vhdlpp: Emit init values for wires as a weak assignment.
2016-03-07 09:54:28 +01:00
Martin Whitaker
Cary R
Stephen Williams
Larry Doolittle
Maciej Suminski
Johann Klammer