7d5f6c551a
Fix unused variable warning and assumed buffer size from last merge.
2016-07-23 12:01:58 +01:00
191811f78f
Merge branch 'conda-fix' of https://github.com/tfors/iverilog
2016-07-23 11:40:09 +01:00
b1b91f49c8
Update vlog95 target to handle timescales for root scope tasks/functions.
2016-07-23 00:10:01 +01:00
27213f2af8
Fix for GitHub issue #115 - synthesis aborts on case with max guard of 0.
...
The calculation of the required multiplexer width was incorrect for
the corner case of a single guard value of zero.
2016-07-22 23:09:36 +01:00
7bed181f68
Support timescales in design units that aren't inside a module.
...
SystemVerilog allows tasks, functions, and classes to be defined at the
root level or inside packages, so we can't rely on an enclosing module
being present to provide the timescale.
2016-07-22 22:48:20 +01:00
e316cc708b
Fix assignment of outputs from class methods.
...
As for inputs, skip over the implicit 'this' parameter.
2016-07-21 19:06:21 +01:00
b8f9ed27c5
Fix for br1003 - prevent segfault when delays are used outside a module.
2016-07-21 08:40:45 +01:00
cada40ebd1
Updated comments
2016-07-18 08:10:41 -05:00
3afbb903d6
Use /proc/self/exe on linux, if it exists, to find ivl_root
2016-07-18 08:05:16 -05:00
43cd693fe0
Put start events to proper queue.
2016-07-17 09:47:08 -07:00
c37d6ac3ac
Merge branch 'master' of github.com:steveicarus/iverilog
...
Conflicts:
vhdlpp/parse_misc.cc
vhdlpp/vtype.cc
2016-07-17 09:36:34 -07:00
ad1101cc80
Fix for br1005 - segfault when SV queue is declared inside a class.
...
For now, output a "sorry" message to indicate this is not yet
supported.
2016-07-11 20:04:24 +01:00
ad87704809
Partial fix for br1006 - allow part selects in path declarations.
...
This just enables the compiler to parse path declarations that
contain part selects. As for bit selects, the part select is
discarded, and if elaboration of specify blocks is enabled,
the path declaration will be applied to the entire vector. If
elaboration is enabled, a warning message will now be output
when a bit or part select is discarded.
2016-07-10 20:00:39 +01:00
7f612270b3
Improved fix for GitHub issue #112 .
...
This does a better job of setting the intermediate expression types
and widths when calculating the canonical index into a packed array.
It still doesn't properly handle out-of-bound indices (br953).
2016-07-10 13:30:58 +01:00
1448210f28
Fix for GitHub issue 112 - index calculation for >2D packed arrays.
2016-07-09 23:33:33 +01:00
d496b095ff
Fix vector width calculation for multi-dimensional packed arrays.
2016-07-09 17:10:22 +01:00
e1ec23d160
Merge pull request #114 from wzab/master
...
Changes necessary to compile with gcc on Debian/Linux testing
2016-07-09 09:04:24 +01:00
2c52fd65d3
Changes necessary to compile with gcc on Debian/Linux testing
2016-07-07 23:01:02 +02:00
6c7495c93e
Merge branch 'master' of github.com:steveicarus/iverilog
2016-07-05 07:59:29 -07:00
f03e9d4180
Merge pull request #113 from CastMi/original_master
...
Checks for pointers
2016-07-05 07:59:16 -07:00
540bb5afa6
Revert "Update parse_misc.cc"
...
This reverts commit 6d06e9351a
2016-07-05 07:56:18 -07:00
f657d1d7d7
Revert "Update vtype.cc"
...
This reverts commit 49515ff62b
2016-07-05 07:56:06 -07:00
70031c9d0f
Merge pull request #111 from forflo/master
...
Resolved #110
2016-07-05 07:50:52 -07:00
0aa5487214
Check pointers before dereferencing
2016-06-30 17:47:34 +02:00
3aa9d535f1
Avoid out of bounds
2016-06-30 17:47:34 +02:00
9ad46044b4
Cleanup
2016-06-30 17:47:34 +02:00
2d7534b005
Implement barrel shifter LPM for BLIF target
2016-06-13 10:55:38 -07:00
31482cbceb
Implement sign extension LPM for BLIF target
2016-06-13 10:51:46 -07:00
2d5a48c579
Support PULLUP/DOWN and BUFZ in BLIF backend
2016-06-13 10:26:46 -07:00
6d06e9351a
Update parse_misc.cc
...
Fixed bug described in #110
2016-06-13 00:56:43 +02:00
49515ff62b
Update vtype.cc
...
Fixed bug described in #110
2016-06-13 00:55:28 +02:00
8234f1845d
Fix for GitHub issue #106 - prevent VPI writes during read-only synch.
2016-06-09 21:27:20 +01:00
332170d36b
Fix for GitHub issue #105 - fully support SV macro escape sequences.
...
The existing support for ``, `", and `\`" did not work in nested macro
definitions. Note that the new implementation only detects and replaces
these sequences inside the macro text (as required by the IEEE standard),
whereas the old implementation would detect and replace them anywhere in
the source files.
2016-06-06 20:12:04 +01:00
45fbf55806
Add basic support for parameters using typedefs
2016-05-14 10:34:50 -07:00
61c82d2cb0
Handle mixed continuous and non-blocking assignments to same vector.
...
SystemVerilog allows a mixture of procedural and continuous assignments
to be applied to different parts of the same vector. The previous attempt
to make this work for non-blocking assignments was flawed (see preceding
fix for vvp_fun_part_pv::recv_vec4_pv). Instead, handle this case by
converting the non-blocking assignment into a delayed force statement,
which matches the way mixed continuous and blocking assignments are
handled.
2016-05-10 22:16:40 +01:00
0c66116f51
Fix for GitHub issue #103 - vvp assertion failure on part select propagation.
...
The implementation of vvp_fun_part_pv::recv_vec4_pv was incorrect, and
propagated the incoming widths rather than the stored widths.
2016-05-10 21:59:21 +01:00
a219df2f18
Merge pull request #95 from orsonmmz/automatic_rebased
...
vhdlpp: Specify lifetime for variables.
2016-05-04 08:05:01 -07:00
6e5ed73b09
Extended fix for GitHub issue #99 .
...
Most vvp functors need to support recv_vec4_pv. Any that are strength-aware
also need to support recv_vec8_pv. Note the simplifying assumption that is
documented in the base class recv_vec4_pv_ implementation.
2016-04-18 23:47:43 +01:00
b2f7d09f0d
Fix GitHub issue #99 - recv_vec4_pv not implemented for arithmetic functors.
...
Also initialise the stored operand values to 'bz instead of 'bx to get
the correct results when bits are not driven.
2016-04-04 22:29:54 +01:00
6ba2bee977
Fix for br974 - support SV types in non-ansi port declarations.
2016-04-04 20:40:30 +01:00
9f88b26a67
Fix vlog95 target to handle delayed CA to vector part select.
2016-04-02 22:24:14 +01:00
20104c92c8
Fix for GitHub issue #96 - support mixed constant/variable delays in vvp.
...
If all three rise/fall/decay delay values are constant, we can use
the vvp .delay statement variant that takes three literal numbers.
If not, we have to use the variant that takes three net inputs. If
some of the delay values are constant, we need to create constant
drivers for those delay inputs.
2016-04-02 19:55:56 +01:00
4521be4510
More spelling, comments only
2016-04-01 11:02:34 -07:00
89edf62206
Capitalize Verilog in a few places
2016-04-01 11:02:24 -07:00
163a913559
vhdlpp: Specify lifetime for variables.
2016-03-29 11:27:14 +02:00
b7d263462c
vhdlpp: Fixed automatic variables initalization in subprograms.
2016-03-29 11:27:14 +02:00
4c82352229
vhdlpp: Corrected the comment mark from the previous commit.
2016-03-29 11:27:14 +02:00
97e31ec9fa
vhdlpp: Workaround to make subprograms work as if they were automatic.
2016-03-29 11:27:14 +02:00
d6ef813a20
vhdlpp: Emit subprograms as automatic by default.
2016-03-29 11:27:14 +02:00
7f475d4210
Refactor to use new pad_to_width/cast_to_width functions.
2016-03-25 22:23:45 +00:00
Martin Whitaker
Thomas Fors
Yury Gribov
Stephen Williams
martinwhitaker
Wojciech M. Zabolotny
Michele Castellana
anon
Cary R
Larry Doolittle
Maciej Suminski