Nick Gasson
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be12f56856
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Document blocking assignment behaviour
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2008-06-18 14:04:16 +01:00 |
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Nick Gasson
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e0f41198d6
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Blocking assignment working correctly
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2008-06-18 13:49:03 +01:00 |
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Nick Gasson
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fb31a88c51
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Blocking assignment nearly working
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2008-06-18 13:30:19 +01:00 |
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Nick Gasson
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254ccb9ccb
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First passing at blocking assignment
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2008-06-18 13:06:27 +01:00 |
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Nick Gasson
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d2bebee9d9
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Refactor before adding blocking assignment
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2008-06-18 12:51:11 +01:00 |
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Nick Gasson
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9fbb449e06
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Optimise away empty (VHDL) processes
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2008-06-13 14:17:24 +01:00 |
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Nick Gasson
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0a8fd50c4a
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Find assignments that could be initializers
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2008-06-13 13:59:48 +01:00 |
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Nick Gasson
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a7cfdc3a87
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Add VHDL if statement to AST types
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2008-06-11 14:11:37 +01:00 |
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Nick Gasson
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d762253f74
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Wait statements
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2008-06-09 12:40:59 +01:00 |
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Nick Gasson
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c3ac1aac8c
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Remove debugging messages from output
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2008-06-04 21:07:50 +01:00 |
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Nick Gasson
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6e448da90d
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Emit Write() calls for parameters of $display
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2008-06-04 15:19:44 +01:00 |
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Nick Gasson
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4bf2e1669d
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Store packages required with entity rather than globally
Add parent link to architecture and process so code generators can push things higher up
$display now prints blank lines
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2008-06-04 13:52:56 +01:00 |
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Nick Gasson
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4211e651d0
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Stub file for processing statements
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2008-06-03 18:26:36 +01:00 |
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Nick Gasson
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a09b4e3b92
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Initial process have wait at the end
(do it properly this time rather than a hack :-)
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2008-06-03 17:39:24 +01:00 |
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Nick Gasson
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ab6ae621cb
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Remove useless comments in output
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2008-06-02 20:24:25 +01:00 |
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Nick Gasson
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9292a087e8
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Generate VHDL processes from Verilog processes
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2008-06-02 16:17:01 +01:00 |
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Nick Gasson
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7c9d154461
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Forgot source files for entity generation
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2008-05-31 15:31:48 +01:00 |