Commit Graph

7957 Commits

Author SHA1 Message Date
Henry Wong ce88deaa97 Fix segfault when error in multi-dimensional part select.
(cherry picked from commit 182c08b528)
2016-11-25 21:33:47 +00:00
Henry Wong 1a8b19baf2 Fix null-pointer when trying to dump null statements.
(cherry picked from commit 69a96112e8)
2016-11-25 21:33:41 +00:00
Henry Wong b3cf533b3c Pop current_block_stack after for_variable_declaration and foreach.
(cherry picked from commit f827e4f748)
2016-11-25 21:33:33 +00:00
Martin Whitaker ba3856ebb0 Fix indentation in previous patch.
(cherry picked from commit 991d7d7582)
2016-10-20 16:49:37 +01:00
Henry Wong c06e2790a7 Adding implementation of NetEvWait::nex_input to handle event controls inside always@(*) blocks
(cherry picked from commit 1f9bf656ed)
2016-10-20 16:49:29 +01:00
Maciej Suminski 6e460a6a3f Fixed warnings about shifting a negative value 2016-10-14 23:41:11 +01:00
Maciej Suminski dbc536c4fb Added missing brackets
(cherry picked from commit 3710d35dd1)
2016-10-14 23:22:26 +01:00
Stephen Williams 5e41c86d01 Merge branch 'v10-branch' of github.com:steveicarus/iverilog into v10-branch 2016-10-14 10:31:58 -07:00
Martin Whitaker 572124e1e9 Allow library files to be specified on the iverilog command line.
This was already supported in command files, using the '-v' flag.
'-v' is already in use on the command line, so use '-l' instead,
and make that an alias for '-v' in command files.

(cherry picked from commit 7ddc514518)
2016-10-02 19:17:24 +01:00
Martin Whitaker 37ecdb4cfb Stop tgt-vvp from generating .alias records.
(partial backport of commit d44c814bab)

Net arrays can be handled by nets directly, instead of creating
.alias records. But keep support for .alias records in vvp. to
maintain backwards compatibility.
2016-09-17 19:49:26 +01:00
Martin Whitaker a11dc8b472 Backport Nexus::has_floating_input() from master branch.
Needed to support check for output port coercion.
2016-09-17 19:40:05 +01:00
Martin Whitaker e7852f8f9c Fix for GitHub issue #127 - coerce output ports to inout when necessary.
(cherry picked from commit 080dd0323d)
2016-09-17 19:24:04 +01:00
Martin Whitaker 9449c46865 Use gn_system_verilog() where appropriate.
Replace explicit comparisons against generation_flag with calls to
the gn_system_verilog helper function, both for code clarity and
to fix a couple of bugs. Also simplify the implementation of the
function, as we already rely on the generation_flag enumeration
being an ordered list.

(cherry picked from commit 3c9b39846c)
2016-09-17 19:23:48 +01:00
Martin Whitaker 8a780ece56 Merge branch 'v10-branch' of github.com:steveicarus/iverilog into v10-branch 2016-08-15 20:49:51 +01:00
Cary R 8bb4777789 Fix getting timeunit outside of module to use a defined check value 2016-08-14 17:26:31 -07:00
Cary R 3b705d95a6 Update fstapi.c to latest from GTKWave 2016-08-14 12:47:15 -07:00
Martin Whitaker f9559853f1 Fix for br1007 - out-of-range constant bit select should be a warning.
An out-of-range constant bit select on the LHS of an assignment was being
treated as an error, whereas an out-of range constant part select would
only result in a warning. In any other context, either case would result
in a warning, so convert the error to a warning.

In addition, all warnings for out-of-range or undefined constant bit/part
selects should be controlled by -Wselect-range.

(cherry picked from commit b51e58fa9d)
2016-08-08 22:26:05 +01:00
Martin Whitaker cda95c1554 Fix vlog95 target to handle hierarchical references in root-level tasks.
(cherry picked from commit 8461e1d9c4)
2016-07-26 22:04:05 +01:00
Martin Whitaker 4066031add Fix for GitHub issue #104 - assigning hierarchical signal from top level task.
When emitting a design, all scopes must be emitted before emitting any
top level task/function/method definitions, otherwise hierarchical
references can't always be resolved.

(cherry picked from commit 2bc42fc6e2)
2016-07-26 22:03:59 +01:00
Martin Whitaker d6d50e9b68 Update vlog95 target to handle timescales for root scope tasks/functions.
(cherry picked from commit b1b91f49c8)
2016-07-23 00:15:55 +01:00
Martin Whitaker 0ffbb2b1de Fix for GitHub issue #115 - synthesis aborts on case with max guard of 0.
The calculation of the required multiplexer width was incorrect for
the corner case of a single guard value of zero.

(cherry picked from commit 27213f2af8)
2016-07-23 00:15:43 +01:00
Martin Whitaker 9b55a3d67f Support timescales in design units that aren't inside a module.
SystemVerilog allows tasks, functions, and classes to be defined at the
root level or inside packages, so we can't rely on an enclosing module
being present to provide the timescale.

(cherry picked from commit 7bed181f68)
2016-07-23 00:15:15 +01:00
Martin Whitaker 07623bef2e Fix assignment of outputs from class methods.
As for inputs, skip over the implicit 'this' parameter.

(cherry picked from commit e316cc708b)
2016-07-23 00:13:07 +01:00
Martin Whitaker 73d688c313 Fix for br1003 - prevent segfault when delays are used outside a module.
(cherry picked from commit b8f9ed27c5)
2016-07-23 00:12:57 +01:00
Martin Whitaker 6155986d1c Fix for br1005 - segfault when SV queue is declared inside a class.
For now, output a "sorry" message to indicate this is not yet
supported.

(cherry picked from commit ad1101cc80)
2016-07-11 20:13:52 +01:00
Martin Whitaker face462cc2 Partial fix for br1006 - allow part selects in path declarations.
This just enables the compiler to parse path declarations that
contain part selects. As for bit selects, the part select is
discarded, and if elaboration of specify blocks is enabled,
the path declaration will be applied to the entire vector. If
elaboration is enabled, a warning message will now be output
when a bit or part select is discarded.

(cherry picked from commit ad87704809)
2016-07-10 20:25:39 +01:00
Martin Whitaker a5f6329500 Improved fix for GitHub issue #112.
This does a better job of setting the intermediate expression types
and widths when calculating the canonical index into a packed array.
It still doesn't properly handle out-of-bound indices (br953).

(cherry picked from commit 7f612270b3)
2016-07-10 13:38:44 +01:00
Martin Whitaker 3e13594816 Fix for GitHub issue 112 - index calculation for >2D packed arrays.
(cherry picked from commit 1448210f28)
2016-07-10 13:38:36 +01:00
Martin Whitaker 99138eafb1 Fix vector width calculation for multi-dimensional packed arrays.
(cherry picked from commit d496b095ff)
2016-07-10 13:38:23 +01:00
Martin Whitaker 86968e3752 Fix for GitHub issue #106 - prevent VPI writes during read-only synch.
(cherry picked from commit 8234f1845d)
2016-06-09 21:29:32 +01:00
Martin Whitaker 27a46f4afe Fix for GitHub issue #105 - fully support SV macro escape sequences.
The existing support for ``, `", and `\`" did not work in nested macro
definitions. Note that the new implementation only detects and replaces
these sequences inside the macro text (as required by the IEEE standard),
whereas the old implementation would detect and replace them anywhere in
the source files.

(cherry picked from commit 332170d36b)
2016-06-06 20:26:52 +01:00
Martin Whitaker d770199550 Add tgt-vvp sorry message for unsupported mixed NB/CA to vector. 2016-05-10 23:02:04 +01:00
Martin Whitaker 06f6a72770 Fix for GitHub issue #103 - vvp assertion failure on part select propagation.
The implementation of vvp_fun_part_pv::recv_vec4_pv was incorrect, and
propagated the incoming widths rather than the stored widths.

(cherry picked from commit 0c66116f51)
2016-05-10 22:41:58 +01:00
Maciej Suminski 30257e0914 ivl: Support for part selection in multidimensional packed ports assignment.
(cherry picked from commit b4baace4b1)
2016-04-19 21:32:38 +01:00
Maciej Suminski b2281b0e65 ivl: Fixed slice base calculation
when range is rising (e.g. logic [0:3] arr) or when it
starts with a non-zero integer (e.g. logic [4:1] arr).

(cherry picked from commit de775975e8)
2016-04-19 21:26:35 +01:00
Maciej Suminski 161cebb178 vvp: Corrected vvp_net_fun_t::recv_vec4_pv() (commit de968e18)
(cherry picked from commit 9cf1dcbae2)
2016-04-19 21:04:48 +01:00
Martin Whitaker b46d8b8389 Fix for br974 - support SV types in non-ansi port declarations.
(cherry picked from commit 6ba2bee977)
2016-04-19 20:47:33 +01:00
Martin Whitaker 2689ebacfe Extended fix for GitHub issue #99.
Most vvp functors need to support recv_vec4_pv. Any that are strength-aware
also need to support recv_vec8_pv. Note the simplifying assumption that is
documented in the base class recv_vec4_pv_ implementation.

(cherry picked from commit 6e5ed73b09)
2016-04-19 20:46:55 +01:00
Martin Whitaker 5bbb054173 Add check for explicit lifetime when initialising static variables.
If a static variable declared in a task, function, or block has an
initialisation expression, SystemVerilog requires the declaration to
have an explicit static lifetime. This is supposed to be a compile
error, but for now just output a warning.

Implementing this required adding support in the parser for explicit
lifetimes in variable declarations. For now, just output an error if
the user asks for a lifetime that isn't the default for that scope.

(cherry picked from commit 9538c81d34)
2016-04-19 20:43:25 +01:00
Martin Whitaker 7d2eeb0137 Added support for default subroutine lifetimes (SystemVerilog).
(cherry picked from commit 6e718c2e0c)
2016-04-19 20:43:14 +01:00
Martin Whitaker 4aef636559 Variable initialization blocks should be unamed.
Also add file/line info to initial process.

(cherry picked from commit 72bb63cf42)
2016-04-19 20:41:48 +01:00
Martin Whitaker 72fc3d712d For SystemVerilog, run variable initialization before main simulation starts.
(cherry picked from commit 54feb89bf5)
2016-04-19 20:41:25 +01:00
Martin Whitaker 3f75f6b155 Fully support variable initialization in tasks/functions/named blocks.
(cherry picked from commit 635adfc01e)
2016-04-19 20:40:14 +01:00
Martin Whitaker 9be3fc3a56 Fix GitHub issue #99 - recv_vec4_pv not implemented for arithmetic functors.
Also initialise the stored operand values to 'bz instead of 'bx to get
the correct results when bits are not driven.

(cherry picked from commit b2f7d09f0d)
2016-04-04 22:41:10 +01:00
Larry Doolittle aa2260f4fa Capitalize Verilog in a few places
(cherry picked from commit 89edf62206)
2016-04-02 22:42:26 +01:00
Martin Whitaker 6974613bff Fix for GitHub issue #96 - support mixed constant/variable delays in vvp.
If all three rise/fall/decay delay values are constant, we can use
the vvp .delay statement variant that takes three literal numbers.
If not, we have to use the variant that takes three net inputs. If
some of the delay values are constant, we need to create constant
drivers for those delay inputs.

(cherry picked from commit 20104c92c8)
2016-04-02 20:04:08 +01:00
Martin Whitaker 8bd4e9d481 Refactor to use new pad_to_width/cast_to_width functions.
(cherry picked from commit 7f475d4210)
2016-03-25 22:42:20 +00:00
Martin Whitaker 04ae07f03c Fix for GitHub issue #94 - enhance support for SystemVerilog size casting.
Allow the size expression to be any constant expression. Also ensure that
the expression width and type are correctly calculated and applied.

(cherry picked from commit dc1c3a4043)
2016-03-25 22:41:50 +00:00
Cary R d9be5318f9 Fix a cppcheck warning 2016-03-24 20:24:03 -07:00
Cary R 88cd5534c4 Use correct type when printing supply pull message 2016-03-15 03:51:39 -07:00