luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix for GitHub issue #127 - coerce output ports to inout when necessary. 

(cherry picked from commit 080dd0323d)
This commit is contained in:
Martin Whitaker 2016-09-17 19:20:48 +01:00
parent 9449c46865
commit e7852f8f9c
1 changed files with 10 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
elaborate.cc
View File

@ -1425,6 +1425,16 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
<< prts[0]->name() << " is coerced to inout." << endl;
}
if (!prts.empty() && (prts[0]->port_type() == NetNet::POUTPUT)
&& (prts[0]->type() != NetNet::REG)
&& prts[0]->pin(0).nexus()->has_floating_input()
&& pins[idx]->is_collapsible_net(des, scope)) {
prts[0]->port_type(NetNet::PINOUT);
cerr << pins[idx]->get_fileline() << ": warning: output port "
<< prts[0]->name() << " is coerced to inout." << endl;
}
// Elaborate the expression that connects to the
// module[s] port. sig is the thing outside the module
// that connects to the port.