Commit Graph

6230 Commits

Author SHA1 Message Date
Martin Whitaker c59d27e19f Remove more clang warnings.
clang warns that the yyinput function generated by flex is never used.
2011-09-25 10:14:16 -07:00
Cary R eab5bacf9f Remove clang/clang++ warnings.
This patch makes the code consistently use struct/class in the C++ files,
it removes a couple shadow warnings and where a class pointer is passed to
the C routines, it defines the pointer as a class for C++ and as struct for
C and it removes a namespace std duplication.
2011-09-25 10:14:04 -07:00
Cary R 609c038484 Add more support for signed enumerations in SV.
This patch add support for passing if the enumeration is signed or not
to the run time. This is really only needed for debug and VPI access.
2011-09-25 09:56:02 -07:00
Stephen Williams 52019b0e55 Merge branch 'master' into work8 2011-09-18 19:48:50 -07:00
Stephen Williams 88cce86c63 Emit code for the to_unsigned() bulit-in function. 2011-09-18 19:31:28 -07:00
Stephen Williams 557e331ce1 Support SystemVerilog size cast. 2011-09-18 19:21:46 -07:00
Stephen Williams 873a447b5c Evaluate VHDL <name>'length attribute at compile time. 2011-09-18 17:45:06 -07:00
Stephen Williams 677a22d353 Generate code for vhdl for loops. 2011-09-18 15:51:31 -07:00
Stephen Williams f0e61a1db7 Basic vhdl elaboration for unary not operator. 2011-09-18 15:13:30 -07:00
Stephen Williams f4217af506 ostream operator for perm_string objects. 2011-09-18 15:12:51 -07:00
Stephen Williams 4d445dc269 Fix parse of unnamed processes. 2011-09-18 09:37:11 -07:00
Alexander Klimov 766bf45dcf Fix long division.
On a 64-bit machine the following module shows incorrect division
results:

`define X {4'b 1000, `N'b 0}
`define Y {1'b  1, `N'b 0}
module b;
   reg [`N:0] y = `Y;
   reg [3:0] z1, z2;
   initial begin
      z1 = `X / `Y;
      z2 = `X /  y;
      $display("%3d %b %b", `N, z1, z2);
   end
endmodule // b

$ for N in {60..65}; do /usr/bin/iverilog -DN=$N -oa b.v && /usr/bin/vvp a; done
 60 1000 1000
 61 1000 1000
 62 1000 0111
 63 1000 0101
 64 1000 1000
 65 1000 1000

The first chunk of the patch (result -> tmp_result) fixes this:

$ for N in {60..65}; do iverilog -DN=$N -oa b.v && vvp a; done
 60 1000 1000
 61 1000 1000
 62 1000 1000
 63 1000 1000
 64 1000 1000
 65 1000 1000

The second chunk fixes

`define X 264'h 800000000000000000000000000000000000000000000000000000000000000000
`define Y 192'h c6df998d06b97b0db1f056638484d609c0895e8112153524
module c;
   reg [191:0] y = `Y;
   reg [72:0] z1, z2;
   initial begin
      z1 = `X / `Y;
      z2 = `X /  y;
      $display("%x %x %b", z1, z2, z1 == z2);
   end
endmodule // c

$ /usr/bin/iverilog -oa c.v && /usr/bin/vvp a
0a4c4a2c1dacd76220c 0809033397ca3427927 0

$ iverilog -oa c.v && vvp a
0a4c4a2c1dacd76220c 0a4c4a2c1dacd76220c 1
2011-09-17 18:35:25 -07:00
Stephen Williams f0bf64271b SystemVerilog has more lax rules for function declarations.
Allow empty parameter lists
Allow lists of statements instead of simple statements.
2011-09-17 12:10:05 -07:00
Stephen Williams 1d02f89a09 Handle vhdh array aggregate expressions.
Support the more general case of explicit element expressions
defined at various index positions, mixed with "others" records.
2011-09-11 17:08:22 -07:00
Stephen Williams 3497e2e663 Distinguish bit selects of entity ports from function calls.
Besides variables and signals, a name with a bit select may
be an entity port. Distinguish these from function calls.
2011-09-11 15:28:58 -07:00
Cary R 64e16d34f3 Add vhdl_sys.vpi to the make clean target 2011-09-11 12:08:06 -07:00
Cary R 8383188292 Add support to dump the two-state variables.
Add support to dump the two-state variables (bit, byte, short, int and
long) using the fst, lxt, lxt2 and vcd dumpers.
2011-09-11 12:07:02 -07:00
Cary R dd9962c221 The two-state variables are in the vpiVariable category.
Add all the two-state variables (bit, byte, short, int and long) to
the vpiVariable category.
2011-09-11 12:04:03 -07:00
Cary R 507621ef30 Update $scanf, $printtimescale and the general is_numeric check for 2-state
This patch updates the $scanf and $printtimescale routines to work with
two-state variables. It also updates the general is_numeric check to
recognize two-state variables as numeric.
2011-09-11 11:58:16 -07:00
Cary R 746a21b437 Update the $random routines to allow an int, long or bit as a seed.
Modify the $random code to allow the seed to be either an int, long or
bit that is 32 bits or longer. The 32 bit check is new and also applies
to reg/logic variables.
2011-09-11 11:58:09 -07:00
Cary R dc0e66ab90 Update $clog2() to add support for two-state variables.
The $clog2() routine can consider any two state variable argument
as numeric.
2011-09-11 11:57:50 -07:00
Cary R 57f296455a The $value$plusargs() routine can put to a two-state variable.
Update the $value_plusargs() routine so it can put the extracted value
to a two-state variable.
2011-09-11 11:57:30 -07:00
Cary R e7a705d8e6 The $queue routines can use two-state variables.
Update the various $queue routines to use the appropriate two-state
variables depending on the context.
2011-09-11 11:57:08 -07:00
Cary R 45d8925ad2 Add the ability to $display and $monitor a bit, byte, short, int or long var.
Add code so that we can $display and $monitor the two-state variables.
2011-09-11 11:53:19 -07:00
Cary R 9fb317a4e1 A vpiBitVar can have a non-zero LSB and can be unsigned.
The general bit variable can be either signed or unsigned and can
have a non-zero LSB.
2011-09-11 11:47:39 -07:00
Cary R 4f8cace5a9 Add the ability to place callbacks on bit, byte, short, int and long variables.
You can place a callback on the new SystemVerilog 2-state variables.
2011-09-11 11:46:25 -07:00
Cary R 40c37be307 Display the type name for bit variable (vpiBitVar).
Display vpiBitVar instead of 620 when asking for the type name of a
bit variable.
2011-09-11 11:42:46 -07:00
Cary R ca6af1c20d Fix some space issues. 2011-09-11 11:41:38 -07:00
Cary R b2ebc29c5a Fix some enum bugs.
This patch fixes a few more bugs in the enumeration code.

It add support for saving the file and line information to make
diagnostic messages better.

It updates some of the compiler warning messages to use the file
and line information.

It passes if the enumeration type is signed all the way to the
code generators.

It fixes the parser to correctly have the range after the signed
designation for the vector types.

It adds a warning that vvp does not currently support a negative
two state enumeration value.
2011-09-11 11:32:16 -07:00
Cary R f3522e98f1 For MinGW driver report an error if the two \\ are not found in the exe path
We need to print a message and fail if the two \\ characters are not found
in the executable path.

Also update the generation warning to include -g2005-sv.
2011-09-11 11:29:12 -07:00
Nick Gasson e49b796a51 Fix for pr3397689.
This is caused by a bug in some simple pattern matching the VHDL target does to try
and produce more idiomatic code in common cases (e.g. FFs with asynchronous resets in
this case). This patch just restricts the kinds of if-statements we use this
optimisation for.
2011-09-11 11:21:07 -07:00
Stephen Williams 563d73e7d9 Index/part select of VHDL l-values changes expression type
The changed expression type impacts how code is generated
for the r-value expression.
2011-09-03 17:57:37 -07:00
Stephen Williams 6d28c989ce Handle the basics of aggregate expressions
This takes care of the parser support, and a shell of the
elaboration. Handle some special cases all the way through.
2011-09-03 17:11:55 -07:00
Stephen Williams 4464c5849b Handle a few built-in functions internally.
The "unsigned" and "std_logic_vector" functions are internal
functions and VHDL and can be handled internally in the code
generator.
2011-08-28 15:30:45 -07:00
Cary R b16401301e For MinGW report an error of the two \\ are not found in the exe path
We need to print a message and fail if the two \\ characters are not found
in the executable path.
2011-08-27 10:04:33 -07:00
Prasad Joshi 95d58cbc42 Real variable support for increment/decrement operator
Signed-off-by: Prasad Joshi <prasad@canopusconsultancy.com>
2011-08-21 17:00:53 -07:00
Prasad Joshi 5311aeaa19 Operand of increment/decrement should not be a number
The patch adds necessary error checking to verify that the operands of
increment decrement operator is not number.

Signed-off-by: Prasad Joshi <prasad@canopusconsultancy.com>
2011-08-21 16:57:23 -07:00
Stephen Williams 7556a37859 Parse function calls, and detect type case expressions.
Type cast expressions and some function calls are syntactically
identical to array element select, so we can only tell the difference
by looking up the name of the identifier being selected. If it is a
type name, then create an ExpCast instead of an ExpName object.

Also, parse and emit vector part selects.
2011-08-21 16:52:18 -07:00
Stephen Williams e6a9b5532a Report some missed emit error count. 2011-08-21 16:40:06 -07:00
Stephen Williams a46c66130b Emit VHDL symbols as escaped identifiers 2011-08-20 12:11:49 -07:00
Stephen Williams 78788d17fe Translate VHDL string literals to bit vectors 2011-08-20 11:11:47 -07:00
Stephen Williams 13c17a2485 Fix broken creation of ExpString. 2011-08-17 20:53:49 -07:00
Stephen Williams f5220c54f1 Handle variables in process statements
Parse variables declared in the declaration section of process
statements, and support variable assignment statements.
2011-08-17 20:19:15 -07:00
Jared Casper 51b1d57f19 Update increment and decrement design dump and comments. 2011-08-14 15:13:13 -07:00
Jared Casper 9b785031f5 Implement SystemVerilog final statements.
Add a new IVL_PR_FINAL process type.

Add a flag to NetScope in_final_ which is set when elaborating the
statement of a final procedure.

Add checks during statement elaboration for invalid statements in a
final procedure, similar to checks for statements in functions.

Do a final check to make sure no final blocks have delays.

In the vvp runtime, use "$final" as the flag for the thread created by
the final procedure.  During compilation, instead of adding such a
thread to the sched_list, add it to a new schedule_final_list that
mirrors the schedule_init_list, but is run at the end of simulation.
2011-08-11 14:31:38 -07:00
Prasad Joshi fa589badd8 Add support for increment and decrement operators
This patch adds support for increment/decrement operators as an
expression. The operations on real and vector slices have been
disabled for now.

These operators can be used as in independent statements. However, the
corresponding support is not added in parser.

Changes since V2:
- Additional error checking in elaboration to deny operation on vector
slices and real (suggested by Martin)

Changes since V1:
- Use 'i' and 'I' for increment (suggested by Cary)
- Evaluate sub-expression once (suggested by Cary and Stev)
- Add necessary checks during elaboration to ensure that the
	expression is valid (suggested Stev)
- Proper width handling with vectors (suggested by Martin)

Signed-off-by: Prasad Joshi <prasad@canopusconsultancy.com>
2011-08-11 14:25:19 -07:00
Prasad Joshi 6a40d9edaa Change the net expression cast from 'i' to 'v'
Icarus uses 'i' in the net expressions for a cast to integer. Replacing
it with 'v' would free the character 'i' that can be used for increment
operators. This changes cast operators to become 'v', '2', and 'r'.

Signed-off-by: Prasad Joshi <prasad@canopusconsultancy.com>
Suggested-by: Cary R. <cygcary@yahoo.com>
2011-08-07 11:40:34 -07:00
Martin Whitaker 5fc1a9c9e0 Fix for pr3368642.v.
The vvp target code generator may not elide a BUFZ if the output of
the BUFZ is connected to a net that is the subject of a procedural
force statement.
2011-08-07 11:15:16 -07:00
Stephen Williams 3e3b83da30 Add some detail on how libraries work. 2011-08-05 12:11:54 -07:00
Stephen Williams 13ecb67717 Add support for vhdl named libraries.
Put libraries in a directory of libraries, support a search path
of library directories, and read those libraries as needed.
2011-07-30 18:18:03 -07:00