Commit Graph

94 Commits

Author SHA1 Message Date
Stephen Williams bf521c7eec
Merge pull request #686 from larsclausen/assignment-pattern-expr
Elaborate array assignment pattern values in the right context
2022-04-17 18:36:18 -07:00
Lars-Peter Clausen a3c329ae84 Add regression tests for evaluating expression within assignment patterns
Check that expressions within assignment patterns are evaluated as if they
were assigned to a variable with the same type as the base type of the
assignment pattern target.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-04-17 09:58:19 +02:00
Lars-Peter Clausen 393c7a3b49 Add a regression test for functions with queue return type
Check that a queue type is supported for the return type of a function.
Make sure that the queue is not cleared in between invocations for
non-automatic functions.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-04-17 09:14:38 +02:00
Lars-Peter Clausen 031fbac5be Add regression tests for signed class properties
Check that the signedness of class properties is handled correctly
  * When sign extending
  * When passing as a value to a system function

Check this for both when accessing the property from within a class method
as well as accessing it on a class object.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-04-14 12:01:23 +02:00
Lars-Peter Clausen 0c123b8498 Add regression tests for methods with signed return values
Check that the signedness of the return value of methods is handled
correctly.
  * When sign extending
  * When passing as a value to a system function

Check this for both methods on user defined class as well as built-in
methods on SystemVerilog types.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-04-14 12:01:23 +02:00
Stephen Williams 752a28598b
Merge pull request #681 from larsclausen/signal-real-type
Use `real_type_t` as the data type for `real` type signals
2022-04-13 22:23:14 -07:00
Stephen Williams 760ecfc44f
Merge pull request #680 from larsclausen/class-static-prop-assign
Handle assignment to static class properties in class methods
2022-04-13 22:20:55 -07:00
Lars-Peter Clausen 4ae2eec275 Add regression test for Verilog AMS abs() with function call argument
Check that the behavior of the Verilog AMS `abs()` function is correct when
its argument is a function call. Check this for both vector as well as real
types.

This test is largely a copy of the existing vams_abs2 test, just replacing
the identifier argument with a function call argument.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-04-12 19:38:34 +02:00
Martin Whitaker 6b5d7a3695 Add regression test for br_gh672. 2022-04-12 16:59:41 +01:00
Lars-Peter Clausen ea55421a07 Add regression test for accessing static class properties
Check that static class properties can be accessed for read and write and
that they are shared between all instances of a class type.

Check that this works for the following 3 cases

 * accessing the static property in a class function or task
 * accessing the static property in a class function or task using `this`
 * accessing the static property on a class object instance

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-04-12 11:45:30 +02:00
Lars-Peter Clausen 338516bc55 Add regression tests for constant recursive functions
Check that constant recursive functions are supported. Check both Verilog
style using assignments to the implicit function return signal and
SystemVerilog style using `return`.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-04-11 22:03:02 +02:00
Lars-Peter Clausen 5b6d8e968d Add regression test for recursive function using `return
Add a regression test that checks that recursive functions using a `return`
statement work correctly.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-04-11 22:03:02 +02:00
Stephen Williams 7c5694e516
Merge pull request #673 from larsclausen/package-no-implicit-var
Require explicit data type for package variable declarations
2022-04-10 15:06:26 -07:00
Stephen Williams 3da5b4cf65
Merge pull request #664 from larsclausen/integer-port
Correctly handle separate port type declaration for integer types
2022-04-10 15:05:48 -07:00
Stephen Williams 070b8af63c
Merge pull request #663 from larsclausen/class-constructor
Small class syntax improvements
2022-04-10 14:56:51 -07:00
Stephen Williams 99eaf007a1
Merge pull request #662 from larsclausen/array-base-type-scope
Elaborate base type of array types in the right scope
2022-04-10 14:56:07 -07:00
Martin Whitaker 50ae8cf552 Add regression test for br_gh674. 2022-04-10 21:58:39 +01:00
Lars-Peter Clausen 35c69366a5 Add regression tests for implicit variable declarations in packages
Check that it is not possible to declare a variable in a package without an
explicit data type for the variable.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-04-09 09:15:23 +02:00
Martin Whitaker 42de9e646a Add regression test for br_gh661 and test for correct $random behaviour. 2022-04-03 19:56:56 +01:00
Lars-Peter Clausen 4c9af1c47a Add regression tests for non-ANSI integer module ports
Check that it is possible to declare the type separately from the direction
for non-ANSI integer, time and atom2 ports. Check that it is possible to
both declare the type before and after the direction.

For integer, time and atom2 types the range specification on the port
direction declaration should be empty, rather than the implicit packed
dimension of the integer type.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-03-28 10:40:25 +02:00
Lars-Peter Clausen 571f222a73 Add additional regression tests for class syntax
Check that it is possible to both declare and call class constructors
without using parenthesis after the `new` keyword.

Check that a non-ANSI port for a class constructor results in an error.

Check that it is possible to invoke a class task through a implicit class
handle (`this` or `super`) without using parenthesis after the task name.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-03-28 10:14:56 +02:00
Lars-Peter Clausen 1a95dafc8d Add regression tests array base type elaboration scope
Check that for typedefs of array, dynamic array and queue types the base
type is elaborated in the right scope. There are separate tests for vector
base type and other base types since these take different paths internally.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-03-28 09:17:24 +02:00
Stephen Williams d480c4d7d0
Merge pull request #659 from larsclausen/typedef-overwrite
Support typedef overwrites with unpacked dimensions and in classes
2022-03-27 15:49:55 -07:00
Stephen Williams 658d4f5eee
Merge pull request #658 from larsclausen/class-in-module
Handle multiple instances of modules with class definitions
2022-03-27 15:48:56 -07:00
Lars-Peter Clausen 315bc1908a Add regression tests for enum base type
Check that the behavior for all sorts of base types for enums is correctly
implemented. Both for valid as well as invalid base types.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-03-25 21:55:34 +01:00
Lars-Peter Clausen 252174d15a Add additional regression tests for typedef overwrites
Check that it is possible to create a typedef of an array type that shadows
an existing typedef in a higher level scope.

Also check that it is possible to create a typedef in a class scope that
shadows an exiting typedef in a higher level scope.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-03-23 10:53:56 +01:00
Lars-Peter Clausen abe5e692ce Add regression test for classes defined in modules
Check that it is possible to have multiple instances of a module
that declares a class and that the class in each module instance
is a unique type that can have dependencies on module parameters.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-03-22 11:53:47 +01:00
Martin Whitaker 2c505f0040 Add regression test for issue #621. 2022-03-21 19:55:15 +00:00
Stephen Williams fc80465b87
Merge pull request #656 from larsclausen/enum-compatibility
Restrict enum compatibility to the same scope
2022-03-20 19:13:56 -07:00
Stephen Williams f73af99ce7
Merge pull request #655 from larsclausen/fix-udp-output-reg
parser: Fix UDP registered output syntax
2022-03-20 19:12:34 -07:00
Stephen Williams af09d86113
Merge pull request #647 from larsclausen/non-ansi-ports
Allow to declare direction after data type for non-ANSI ports
2022-03-20 19:10:49 -07:00
Lars-Peter Clausen 83da384df3 Add regression test for enum compatibility across module boundaries
Check that the compatibility of signals of enum data type across module
boundaries.

If the enum data type is declared at a higher level scope or imported from
a package the signals are compatible between different module instances. If
the enum data type is declared within the module itself though the signals
are not compatible.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-03-19 17:17:21 +01:00
Lars-Peter Clausen c5e160f1dd Add regression test for `output reg` syntax for UDPs
Check that it is possible to declare a registered output of a user defined
primitive using the `output reg` syntax.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-03-19 13:00:04 +01:00
Martin Whitaker e53b2e774b Further fixes for vvp code generation for c. assign of an array word.
The draw_net_input() function can write additional statements to the output
file, so must not be called in the midst of writing a statement.
2022-03-19 10:22:49 +00:00
Lars-Peter Clausen db33dbfbcc Add regression tests for task non-ANSI port declarations
Check that it is possible to define the data type of a non-ANSI task port
in a separate declaration from the port direction. Add tests for both the
type declared before the port direction and for the type declared after the
port direction.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-03-16 09:17:55 +01:00
Lars-Peter Clausen ee81ac2f85 Add regression tests for module non-ANSI port declarations
Check that it is possible to define the data type of a non-ANSI module port
in a separate declaration from the port direction. Add tests for both the
type declared before the port direction and for the type declared after the
port direction.

Note that this doesn't work yet correctly for integer type module ports
yet, so there are no tests for this. This will be addressed in follow up
work.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-03-16 09:17:55 +01:00
Martin Whitaker 831db5a0d7 Fix vvp code generation for c. assign shift of array word (issue #632) 2022-03-14 23:24:20 +00:00
Stephen Williams 15e1a7a3f2
Merge pull request #644 from larsclausen/port-range-mismatch-recover
Recover from port and signal vector range mismatch
2022-03-13 14:36:31 -07:00
Stephen Williams d7e4d209b8
Merge pull request #640 from larsclausen/darray-packed-array
Support dynamic arrays and queues of packed arrays
2022-03-13 14:33:27 -07:00
Lars-Peter Clausen a9c0469b2b Add regression test for task port range mismatch
Check that a range mismatch is detected for non-ANSI task ports when
port direction and data type are declared separately.

An error should be reported and no crash should occur.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-03-13 11:17:27 +01:00
Lars-Peter Clausen 026d552be1 Add regression test for module port range mismatch
Check that a range mismatch is detected for non-ANSI module ports when port
direction and data type are declared separately.

An error should be reported and no crash should occur.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-03-13 11:07:10 +01:00
Lars-Peter Clausen 1a10abeae7 Add regression tests for queue of packed arrays
Check that queues of packed arrays are supported. These tests are identical
to the existing queue tests for other data type, just that the data type
is a packed array.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-03-12 14:07:06 +01:00
Lars-Peter Clausen babfacee9a Add regression test for dynamic arrays of packed arrays
Check that it is possible to declare a dynamic array of a packed array
type. The test is identical to the tests for the other supported dynamic
array types.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-03-12 14:07:06 +01:00
Lars-Peter Clausen 5cc825f45d Support dynamic arrays and queues of packed arrays
Currently only dynamic arrays and queues of atom2 and vector types are
supported. Add support for packed arrays. Since these three types are
essentially handled the same internally supporting this only requires to
allow to elaborate a packed array base type.

Factor out type elaboration into a helper function that can be shared
between the elaboration of the base type of a dynamic array or queue and
the type for other signals. This gives consistent behavior and will also
make it easier to support additional base types for dynamic arrays or
queues.

Note that it is not yet possible to index elements of packed array dynamic
arrays or queues. But neither is it possible to do a bit select for vector
or atom2 type dynamic arrays or queues yet. Supporting this needs some
additional work.

There is one test that declares a queue of a struct type, but doesn't use
it since it is not supported. With this change a error will generated when
trying to declare a queue of a struct. So update that test to not declare
the variable so it does not fail.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-03-12 14:07:06 +01:00
Lars-Peter Clausen 9fd91a8df8 Add regression test for empty class item
Check that the empty class item is supported by the parser.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-03-11 21:34:06 +01:00
Stephen Williams ede341410f
Merge pull request #636 from steveicarus/string-special-characters
String special characters
2022-03-05 19:12:16 -08:00
Stephen Williams d2ac403415 Add sv_string7 and sv_stting7b tests.
These test string assignments of various escaped special characters.
2022-03-05 18:49:37 -08:00
Lars-Peter Clausen 41b4ce5f8c Add regression test for part select on vector declared in package
Check that it is possible to do a part select on a vector declared in a
package.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-03-05 15:29:34 +01:00
Lars-Peter Clausen 8a2d4e4fa4 Add regression test for Verilog data types on module input ports
Using Verilog data types on module input and inout ports is an error in
Verilog. But in SystemVerilog it is allowed and the port should be a net
with the specified data type.

Check that this is supported.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-03-03 10:49:59 +01:00
Lars-Peter Clausen 2921e66105 Add regression test for invalid net data types
Add regression tests that check that declaring a net of type class, dynamic
array, queue or string result in an error.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-03-03 10:30:28 +01:00