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11 Commits

Author SHA1 Message Date
Stephen Williams 8580ceea4d Parse component declarations / parse signal declarations. 
These go into the architecture/block of their scope and will be
used by component instantiations to make sure the bindings are
correct and complete.

Also handle signal declarations. The elaborator will use these
to generate module local variables that are used by the architecture.
 2011-03-22 09:18:20 -07:00
Stephen Williams f32ede23b7 Do type mapping in the parser. 
In VHDL, types are declared before they are used, so it is possible
to do type binding during parse. This makes the parser a little bit
cleaner.
 2011-02-13 16:54:56 -08:00
Stephen Williams f138b0d631 Be more precide about mappings to Verilog types. 
Make std_logic map to Verilog logic, and integers and bits map
to Verilog bool. These are more precise and accurate.
 2011-02-13 16:48:52 -08:00
Stephen Williams b08ab3448e Emit net declarations. 
Rather then leave net types to implicit declarations, write
declarations explicitly. This will become necessary when more
interesting types are supported.
 2011-02-13 16:48:52 -08:00
Stephen Williams 5914617727 Clean up entity interface. 2011-02-13 16:48:52 -08:00
Stephen Williams 798ead9345 Code generator for architectures. 
Separate elaboration from code generation in the Entity, and add
to Architectures a code generator to handle some simple cases. At
this point we have the basic structure for the VHDL compiler.
 2011-02-13 16:48:52 -08:00
Stephen Williams 30d689016a Create an Architecture class and bind them to their entities. 2011-02-13 16:43:04 -08:00
Stephen Williams ab8f623cea Add file/line information to entities and ports 
Include the compiler infrastructure to vhdlpp for collecting the
file and line information and attaching it to entities and ports.
Make the parser store the file name during parse.

Create a libmisc library where I can put source files that are
used by multiple programs within the source tree.
 2011-01-18 17:03:51 -08:00
Stephen Williams d72f7ea249 Save the type name if an InterfacePort object. 2011-01-18 17:03:51 -08:00
Stephen Williams 5a6d07ff9f Emit Verilog stubs for entities 
The verilog includes the module declaration with correct ports
in the correct order. Get the port directions correct.
 2011-01-18 17:03:51 -08:00
Stephen Williams 02820c9e34 Parse create entities with ports 
Create entity objects from entity declarations in the source,
and populate them with ports.
 2011-01-18 17:03:51 -08:00