Commit Graph

12 Commits

Author SHA1 Message Date
steve a64a33e65a Full case support 1999-09-29 18:36:02 +00:00
steve 470b0d3d34 Support in vvm > and >= behavioral operators. 1999-09-28 01:13:15 +00:00
steve 2d0e11283d Convert vvm to implement system tasks with vpi. 1999-08-15 01:23:56 +00:00
steve 7400ece69c Add init to vvm_signal_t. 1999-06-21 01:02:34 +00:00
steve 66ac537c43 Implement the < binary operator. 1999-06-07 03:40:22 +00:00
steve 9e82ed240c Restore support for wait event control. 1999-05-03 01:51:29 +00:00
steve d3350c9b27 Add to vvm proceedural memory references. 1999-04-22 04:56:58 +00:00
steve 51b4f70c8f Add some logical operators. 1999-03-16 04:43:46 +00:00
steve fef81958bc Do not generate code for signals,
instead use the NetESignal node to
 generate gate-like signal devices.
1999-02-08 03:55:55 +00:00
steve 4e2c0036aa VVM support for small sequential UDP objects. 1998-12-17 23:54:58 +00:00
steve 7859de1e4e Add support it vvm target for level-sensitive
triggers (i.e. the Verilog wait).
 Fix display of $time is format strings.
1998-11-10 00:48:31 +00:00
steve 8705aa94c6 Add vvm library. 1998-11-09 23:44:10 +00:00