Commit Graph

172 Commits

Author SHA1 Message Date
Stephen Williams 677a22d353 Generate code for vhdl for loops. 2011-09-18 15:51:31 -07:00
Stephen Williams 4d445dc269 Fix parse of unnamed processes. 2011-09-18 09:37:11 -07:00
Stephen Williams 3497e2e663 Distinguish bit selects of entity ports from function calls.
Besides variables and signals, a name with a bit select may
be an entity port. Distinguish these from function calls.
2011-09-11 15:28:58 -07:00
Stephen Williams 6d28c989ce Handle the basics of aggregate expressions
This takes care of the parser support, and a shell of the
elaboration. Handle some special cases all the way through.
2011-09-03 17:11:55 -07:00
Stephen Williams 4464c5849b Handle a few built-in functions internally.
The "unsigned" and "std_logic_vector" functions are internal
functions and VHDL and can be handled internally in the code
generator.
2011-08-28 15:30:45 -07:00
Stephen Williams 7556a37859 Parse function calls, and detect type case expressions.
Type cast expressions and some function calls are syntactically
identical to array element select, so we can only tell the difference
by looking up the name of the identifier being selected. If it is a
type name, then create an ExpCast instead of an ExpName object.

Also, parse and emit vector part selects.
2011-08-21 16:52:18 -07:00
Stephen Williams f5220c54f1 Handle variables in process statements
Parse variables declared in the declaration section of process
statements, and support variable assignment statements.
2011-08-17 20:19:15 -07:00
Stephen Williams f2629d53a2 Add VHDL support for named libraries
Named libraries are similar to the work library, but they are not
written to implicitly, or imported implicitly. They are only brought
in by a "library" clause, the the packages within the library are
brought in by a "use" clause.
2011-07-30 15:04:07 -07:00
Cary R de356b03c8 Fix most of the cppcheck warnings in the vhdlpp directory.
Mostly using size() vs empty() in the STL and a missing initialization.
2011-07-30 09:35:12 -07:00
Cary R 836e61e878 Fix spacing issues in the code.
Remove space at the end of line and space before tab since they serve
no purpose.
2011-07-30 09:33:28 -07:00
Stephen Williams 116d9f5f54 Merge branch 'master' into work7 2011-07-24 11:06:22 -07:00
Pawel Szostek 50f7e1b69e Add parser cleanup to vhdlpp
This commit adds removal of global objects in
the execution of vhdlpp. This includes deleting
design entities and the global parse scope.
2011-07-24 10:03:03 -07:00
Pawel Szostek 3764216a88 Use stl stack for for carrying scopes
This is rather a cosmetic change. The patch changes
the container used for stack of scopes from std::list
to std::stack. It suits this particular application
a bit better.
2011-07-24 09:50:31 -07:00
Pawel Szostek 21008f2ba9 Add missing or fix existing deletes in VHDL parser
Thanks to valgrind analysis it turned out that
there were objects in the parser that were not being
deleted in a proper way. This patch fixes them all.
2011-07-24 09:47:41 -07:00
Stephen Williams df8efed22b Parse work library for imported packages
When a "use" clause tries to pull a package from the work library,
put together a file name and try to find that package in the
work library directory. If found, parse the package file and
try again to find the package.
2011-07-23 10:07:20 -07:00
Stephen Williams 3ef1d01ad1 Rework parse/lex API to be reentrant
Bison and Flex generate different interfaces for reentrant
parsers, so handle that different API. We need this change
because library support is going to reuse the parser to
read in library packages.
2011-07-22 20:49:57 -07:00
Pawel Szostek 60deb775ca Add support for VHDL's loop statements 2011-07-12 19:20:04 -07:00
Pawel Szostek b376115e15 Add parser support for VHDL's null statements
Handle null statements in sequences of statements.
If a null is encountered, it is omitted and not
added to the list of statements.
2011-07-08 18:14:00 -07:00
Pawel Szostek ad31eaaea8 Add parser support for VHDL's procedure call
Parse procedure calls and put them into
abstract syntax tree. Elaboration and emission
still has to be done.
2011-07-08 18:10:30 -07:00
Pawel Szostek 721f9d5d9b Add String Expression to the VHDL parser 2011-07-08 18:05:06 -07:00
Pawel Szostek 88760b9982 Fix case-when VHDL statement 2011-07-08 17:59:55 -07:00
Pawel Szostek 5934dcc17c Add parser support for vhdl's case-when
Case-when statements are now recognized and
turned into corresponding objects. Elaboration
and emission is still not done.
2011-06-30 19:57:27 -07:00
Pawel Szostek bff0927db0 Add remaining tokens to vhdl lexor 2011-06-30 19:36:24 -07:00
Stephen Williams 41601696cc properly handle vhdl open ports in component instantiations. 2011-06-12 16:59:07 -07:00
Stephen Williams bf40c8ecc5 Conditional statements and expressions
Elaborate and emit a variety of conditional constructs.
Fix up type handling for some expression types
Elaborate continuous signal assignments.
2011-06-12 10:51:31 -07:00
Stephen Williams 2e28782af3 Add parser support for concatenations/conditional assignment/elsif
Some of these should be easy to translate, but get the parsing out
of the way first.
2011-06-05 13:58:54 -07:00
Stephen Williams fc25ccde06 Basic emit of sequential code
Infrastructure for debug and emit of sequential statements in processes.
This does not properly handle the actual semantics of the behavioral
code, but it provides an infrastructure where we can handle all the
tricky elaboration to come.
2011-05-15 11:07:42 -07:00
Stephen Williams 3e419dc854 Parse/decorate sequential statements.
Get to the point where our sample program parses completely, and
the sequential statements generate SequentialStmt objects and a
process object in the architecture.

Also add a few missing expression types.
2011-05-08 16:40:35 -07:00
Stephen Williams 7afd4210db Parse some sequential statements and processes. 2011-05-08 13:51:21 -07:00
Cary R 12df29af55 Fix space issues.
Thsi patch removes space before end of line, etc.
2011-04-20 17:26:52 -07:00
Stephen Williams 3ff7a8f7b0 Add support for constants and package types.
Significant rework of scope management to unify the handling of
types in the ieee library and types/constants/components in packages.
This involved adjusting the parser rules to manage a stack of scopes
and rewriting the IEEE library support to not use global maps for
the loaded types.
2011-04-17 17:19:09 -07:00
Stephen Williams 303f057de1 Support collecting ALL component declarations from a used scope. 2011-04-13 19:55:18 -07:00
Stephen Williams d4c5cfc584 Add packages and component declarations within those packages.
This creates the Package class to represent packages, and the
Scope class to represent scopes in general. The library functions
are worked up to support scanning scopes for declarations that are
imported by "use" clauses.
2011-04-13 18:30:00 -07:00
Stephen Williams 791adfab68 Check ports match up in component instantiations.
Make sure in a conponent instantiation that the instantiated
component is really declared, and that the ports of the binding
really do match the ports of the declared component. This requires
that we create and save component declarations, and that components
have methods for mapping the ports.
2011-04-10 09:42:22 -07:00
Pawel Szostek 9bdc040520 Add missing ``sorry'' messages in VHDL parsing 2011-04-02 09:30:36 -07:00
Pawel Szostek cef37e0a4b Add component specification parsing
A class for component specification has been added
2011-04-02 09:29:42 -07:00
Pawel Szostek 830b7cf122 Add basic instantiation list handling in VHDL
A class for representing instantiation list has
been added.
2011-04-02 09:27:58 -07:00
Pawel Szostek 2af35040cc Fix constructs sequence in bison file for VHDL 2011-04-02 09:24:34 -07:00
Pawel Szostek 26e6865bef Add entity aspects to VHDL parsing
Entity aspects are now recognized and parsed
into corresponding objects. A new class (entity_aspect)
has been added.
2011-04-01 17:03:45 -07:00
Stephen Williams abb03632dd Basic elaboration of vhdl component instantiations.
This gets us as far as emiting a component instantiation. Very little
error checking/elaboration is done, so there is room for improvement,
but this is a working stub.
2011-03-31 19:07:43 -07:00
Pawel Szostek 37d6de344d Add use clause parsing
Up till now only "global" use clauses were parsed
and as a result libraries were loaded.

Since use clauses can appear not only in global context,
parsing of non-global clauses has been introduced and
selected names are now handled (like name1.name2.name3).
2011-03-31 18:57:25 -07:00
Stephen Williams 162b26c101 Add more complete support for vhdl local signals.
These signals are declared in the architecture and are local to
the module. The Architecture already parsed and stored these signal
declarations, but this patch adds the ability to actually emit these
signals in the generated code.

In the process of doing this, I had to regularize the elaboration
and emit of VTypes, so that it can be used in multiple places, not
just in entity headers (for ports).

I also added support for bit selects of signals. This effected a couple
places in the parser, and expressions in general.
2011-03-28 14:34:02 -07:00
Pawel Szostek f057ce0859 Basic VHDL configuration parsing
The bison grammar has been extended in order
to parse configuration statements. Parsing
remains very primitive but principal constructs
can be now recognized.
2011-03-28 14:29:06 -07:00
Pawel Szostek ce5c263b4a Simplify entity parsing (removed the duplicate code) 2011-03-23 11:59:02 -07:00
Stephen Williams 8580ceea4d Parse component declarations / parse signal declarations.
These go into the architecture/block of their scope and will be
used by component instantiations to make sure the bindings are
correct and complete.

Also handle signal declarations. The elaborator will use these
to generate module local variables that are used by the architecture.
2011-03-22 09:18:20 -07:00
Stephen Williams 89aa08e1aa Add parser support for architecture declaratives and component instantiations
Also include support for "sorry" messages so that we have a place
to hang unsupported but properly parsed constructs.

In the process of doing this, I also encountered and add parser support
for indexed names. And matching "sorry" messages.
2011-03-22 09:18:01 -07:00
Stephen Williams 2b7323f2c2 Support vhdl identifier lists in interface elements.
syntax like this is ok:

  name1, name1, name3 : in bit;
  name4 : out bit;

and so on.
2011-03-22 09:17:40 -07:00
Stephen Williams 9330b58a3a Merge branch 'master' into work4
Conflicts:
	vhdlpp/lexor.lex
	vhdlpp/parse.y
	vhdlpp/vhdlint.cc
2011-03-14 17:34:57 -07:00
Cary R 2a0d33608f Fix spacing problems.
This patch fixes spacing problems in the source code, space/tab at
the end of line and space before tab.
2011-03-03 11:21:31 -08:00
Stephen Williams e172b4d9bc Add support for unary abs and not operators.
While I'm at it, do a little refactoring of the handling of binary
expressions to reduce code duplication.
2011-02-20 17:03:46 -08:00
Stephen Williams cbb213d79e Support for some arithmetic operators. 2011-02-19 17:47:30 -08:00
Stephen Williams c6ea2f3bf5 Stub support for "use" directives.
Implement the parser infrastructure for handling library use clauses,
and use that to handle specific packages of the ieee library. Make
the numeric types come from the numeric_* packages instead of being
built in.
2011-02-19 13:08:26 -08:00
Stephen Williams 8a5225e61f Stub support for library import.
This provides a stub implementation for library import. Use this
stub to make up a slightly more functional ieee library implementation.
2011-02-19 11:39:00 -08:00
Stephen Williams 7d552980a6 Elaborate array subtypes of ports.
There are internal types that are unbounded arrays. Allow subtype
syntax that creates bounded versions of these arrays, and elaborate
them as vectors at port boundaries. This makes some interesting types
work out.

Also start replacing vhdlint and vhdlreal with int64_t and double,
which are reasonable values for universal_integer and universal_real
from the VHDL standard. I need these cleaned up because the ints in
particular are used for the literal expressions in array index constraints.
2011-02-13 19:01:21 -08:00
Stephen Williams f32ede23b7 Do type mapping in the parser.
In VHDL, types are declared before they are used, so it is possible
to do type binding during parse. This makes the parser a little bit
cleaner.
2011-02-13 16:54:56 -08:00
Stephen Williams d8d56bc569 Architecture syntax allows for closing name. 2011-02-13 16:48:52 -08:00
Stephen Williams 5914617727 Clean up entity interface. 2011-02-13 16:48:52 -08:00
Stephen Williams 769159d053 Add parse decorations for expressions.
Elaboration will need a parse tree for expressions. Create one for
the expression types that are currently supported. Also add rules
and the keywords for all the remaining binary logical operators.
2011-02-13 16:47:05 -08:00
Stephen Williams 3ca0a482cf Annotate the parse of simple concurrent statements. 2011-02-13 16:43:45 -08:00
Stephen Williams 30d689016a Create an Architecture class and bind them to their entities. 2011-02-13 16:43:04 -08:00
Pawel Szostek 77a346ffb1 Added full number, based number (both int and float), string and character literals handling 2011-02-10 18:34:38 -08:00
Pawel Szostek 0395eadbc8 Introductory changes for numbers handling 2011-02-10 18:34:13 -08:00
Pawel Szostek 75203dc121 Minor changes to VHDL lexor 2011-02-10 18:33:53 -08:00
Pawel Szostek d747859a85 New compound VHDL symbols 2011-02-10 18:33:34 -08:00
Pawel Szostek ac28743eb0 New keywords to lexer added and typos corrected 2011-02-10 18:33:07 -08:00
Stephen Williams 9229256f6f Fix identation style. 2011-01-26 17:44:58 -08:00
Pawel Szostek 7eddaaf5bf Entity parsing changed 2011-01-26 17:43:26 -08:00
Stephen Williams ab8f623cea Add file/line information to entities and ports
Include the compiler infrastructure to vhdlpp for collecting the
file and line information and attaching it to entities and ports.
Make the parser store the file name during parse.

Create a libmisc library where I can put source files that are
used by multiple programs within the source tree.
2011-01-18 17:03:51 -08:00
Stephen Williams d72f7ea249 Save the type name if an InterfacePort object. 2011-01-18 17:03:51 -08:00
Stephen Williams 02820c9e34 Parse create entities with ports
Create entity objects from entity declarations in the source,
and populate them with ports.
2011-01-18 17:03:51 -08:00
Stephen Williams 04b239a5fb Flesh out VHDL parser engine.
Add enough rules to parse a simple VHDL program:
  Parse library and use clauses,
  Parse entity declarations, and
  Parse architecture bodies.

Add some parser infrastructure:
  Handle syntax errors with useful error messages,
  Include file name and line numbers in parse errors,
  Add some parser debug aids.
2011-01-18 17:03:51 -08:00
Stephen Williams 8cf1fd1820 Introduce shell of vhdlpp program.
Create the makefiles and configuration scripts to hold together
the vhdlpp front-end program. Create a shell main.
2011-01-18 17:03:51 -08:00