f7d62b96aa
whoops, wrong copyright notice.
2000-11-21 03:55:20 +00:00
197ed46b26
configure bindir and libdir
2000-11-11 00:48:35 +00:00
23a5bd072d
Remove the compiled in Verilog target.
2000-10-28 22:35:58 +00:00
10fbb2a1bb
Glitches in cygwin build process.
2000-10-28 19:12:43 +00:00
72229abda6
check explicitly uses local libraries.
2000-10-28 17:51:45 +00:00
431228e881
make check target (PR#3)
2000-10-28 03:58:11 +00:00
90ae46476c
Makefile patches to support target loading under cygwin.
2000-10-15 21:02:08 +00:00
5ce28c193a
iverilog with an iverilog.conf configuration file.
2000-10-08 22:36:55 +00:00
41f3ba65a1
xor and constant devices.
2000-10-05 05:03:01 +00:00
9680de25cd
Fix the clean target and excess dependencies.
2000-10-04 17:08:31 +00:00
b34a451cbc
Cygwin port changes from Venkat
2000-09-30 03:20:47 +00:00
80c69d565b
Add enough tgt-verilog code to support hello world.
2000-09-23 05:15:07 +00:00
13c1378666
Remember to make the includedir.
2000-09-20 01:02:13 +00:00
effc84c46d
Get the structure for ivl_statement_t worked out.
2000-09-18 01:24:32 +00:00
89d7176734
Add support for modulus (Eric Aardoom)
2000-09-17 21:26:15 +00:00
b6ce313e91
move lval elaboration to PExpr virtual methods.
2000-09-09 15:21:26 +00:00
ac81f6a201
Rearrange NetAssign to make NetAssign_ separate.
2000-09-02 20:54:20 +00:00
d0fc6d515d
Add ivl_target support for logic gates, and
...
make the interface more accessible.
2000-08-20 04:13:56 +00:00
566aad9e15
Start stub for loadable targets.
2000-08-12 16:34:37 +00:00
42e4ff47c8
Move inital value handling from NetNet to Nexus
...
objects. This allows better propogation of inital
values.
Clean up constant propagation a bit to account
for regs that are not really values.
2000-07-14 06:12:56 +00:00
79ca317c1d
Better handle failures to build lexor_keyword.cc
2000-07-11 23:07:28 +00:00
18eb34921f
Add support for non-constant delays in delay statements,
...
Support evaluating ! in constant expressions, and
move some code from netlist.cc to net_proc.cc.
2000-07-07 04:53:53 +00:00
583868e74e
Redesign Links to include the Nexus class that
...
carries properties of the connected set of links.
2000-06-25 19:59:41 +00:00
bec4a205ec
Do not install bin/verilog.
2000-06-16 18:59:49 +00:00
3d85c66b02
Do not install obsolete verilog script.
2000-06-07 03:52:55 +00:00
3c9902d93e
Use yacc based synthesizer.
2000-05-13 20:55:47 +00:00
b44abcd481
Get rid of gverilog source.
2000-05-12 05:23:15 +00:00
367db72c99
Add support for procedural continuous assignment.
2000-05-11 23:37:26 +00:00
e9742c662b
no need for nobufz functor.
2000-05-08 05:29:43 +00:00
f95b082339
More features of ivl available through iverilog.
2000-05-03 22:14:31 +00:00
1db70a0c46
Move signal elaboration to a seperate pass.
2000-05-02 16:27:38 +00:00
b175e4aef7
Better inc and lib paths for iverilog.
2000-05-01 23:55:22 +00:00
08e9a114a2
Catch memory word parameters to tasks.
2000-04-28 16:50:53 +00:00
1412eb2697
iverilog man page.
2000-04-26 20:53:21 +00:00
c0d51dd2eb
Add the iverilog driver program.
2000-04-21 06:41:02 +00:00
2094a2f466
Catch some simple identity compareoptimizations.
2000-04-20 00:28:03 +00:00
4493e968da
Finally remove the NetNEvent and NetPEvent classes,
...
Get synthesis working with the NetEvWait class,
and get started supporting multiple events in a
wait in vvm.
2000-04-12 20:02:52 +00:00
30e8289239
Simulate named event trigger and waits.
2000-04-04 03:20:15 +00:00
2dd010dc04
Named events as far as the pform.
2000-04-01 19:31:57 +00:00
d97ab9be23
New and improved combinational primitives.
2000-03-29 04:37:10 +00:00
649ce73047
Minor performance boost for gperf keyword table.
2000-03-21 05:08:32 +00:00
2563e2b717
Revise the VVM backend to use nexus objects so that
...
drivers and resolution functions can be used, and
the t-vvm module doesn't need to write a zillion
output functions.
2000-03-16 19:03:03 +00:00
6eef54595f
Support localparam.
2000-03-12 17:09:40 +00:00
e7efc2709a
Redesign the implementation of scopes and parameters.
...
I now generate the scopes and notice the parameters
in a separate pass over the pform. Once the scopes
are generated, I can process overrides and evalutate
paremeters before elaboration begins.
2000-03-08 04:36:53 +00:00
ce0b97a8f0
Fix up compiling with configured -ldl switch.
2000-02-05 06:40:35 +00:00
e6bd088984
Compile time problems with vpi_user.h
2000-01-23 23:54:36 +00:00
bed47a4ab4
Make the library install directory.
2000-01-09 17:43:28 +00:00
4c274223cf
Move ivl and ivlpp to the lib directory.
2000-01-01 20:57:50 +00:00
7033836e01
Remove the now useless sigfold functor.
1999-12-30 17:37:13 +00:00
22c2625ace
Add the gverilog driver program.
1999-12-18 04:15:01 +00:00
steve