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More features of ivl available through iverilog.

This commit is contained in:
steve 2000-05-03 22:14:31 +00:00
parent 0a70a8a954
commit f95b082339
4 changed files with 80 additions and 9 deletions
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3
Makefile.in
View File

@ -18,7 +18,7 @@
# 59 Temple Place - Suite 330
# Boston, MA 02111-1307, USA
#
#ident "$Id: Makefile.in,v 1.50 2000/05/02 16:27:38 steve Exp $"
#ident "$Id: Makefile.in,v 1.51 2000/05/03 22:14:31 steve Exp $"
#
#
SHELL = /bin/sh
@ -138,6 +138,7 @@ $(bindir)/verilog: ./verilog
$(bindir)/iverilog: ./iverilog
$(INSTALL_PROGRAM) ./iverilog $(bindir)/iverilog
$(STRIP) $(bindir)/iverilog
$(libdir)/ivl/ivl: ./ivl
$(INSTALL_PROGRAM) ./ivl $(libdir)/ivl/ivl

39
iverilog.c
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
#ident "$Id: iverilog.c,v 1.8 2000/05/01 23:55:22 steve Exp $"
#ident "$Id: iverilog.c,v 1.9 2000/05/03 22:14:31 steve Exp $"
#endif
#include <stdio.h>
@ -34,8 +34,11 @@ const char*opath = "a.out";
const char*targ = "vvm";
const char*start = 0;
char warning_flags[16] = "";
char*f_list = 0;
int synth_flag = 0;
int verbose_flag = 0;
char tmp[4096];
@ -44,7 +47,7 @@ static int t_null(char*cmd, unsigned ncmd)
{
int rc;
sprintf(tmp, " | %s/ivl ", base);
sprintf(tmp, " | %s/ivl %s", base, warning_flags);
rc = strlen(tmp);
cmd = realloc(cmd, ncmd+rc+1);
strcpy(cmd+ncmd, tmp);
@ -88,7 +91,9 @@ static int t_vvm(char*cmd, unsigned ncmd)
{
int rc;
sprintf(tmp, " | %s/ivl -o %s.cc -tvvm -Fcprop -Fnodangle -fVPI_MODULE_PATH=%s", base, opath, base);
sprintf(tmp, " | %s/ivl %s -o %s.cc -tvvm -Fcprop %s -Fnodangle"
" -fVPI_MODULE_PATH=%s", base, warning_flags, opath,
synth_flag?"-Fsynth":"", base);
rc = strlen(tmp);
cmd = realloc(cmd, ncmd+rc+1);
@ -147,7 +152,8 @@ static int t_xnf(char*cmd, unsigned ncmd)
{
int rc;
sprintf(tmp, " | %s/ivl -o %s -txnf -Fcprop -Fsynth -Fnodangle -Fxnfio", base, opath);
sprintf(tmp, " | %s/ivl %s -o %s -txnf -Fcprop -Fsynth "
"-Fnodangle -Fxnfio", base, warning_flags, opath);
rc = strlen(tmp);
cmd = realloc(cmd, ncmd+rc+1);
@ -182,6 +188,20 @@ static int t_xnf(char*cmd, unsigned ncmd)
return rc;
}
static void process_warning_switch(const char*name)
{
if (warning_flags[0] == 0)
strcpy(warning_flags, "-W");
if (strcmp(name,"all") == 0) {
strcat(warning_flags, "i");
} else if (strcmp(name,"implicit") == 0) {
if (! strchr(warning_flags+2, 'i'))
strcat(warning_flags, "i");
}
}
int main(int argc, char **argv)
{
char*cmd;
@ -190,7 +210,7 @@ int main(int argc, char **argv)
int opt, idx;
char*cp;
while ((opt = getopt(argc, argv, "B:Ef:o:s:t:v")) != EOF) {
while ((opt = getopt(argc, argv, "B:Ef:o:Ss:t:vW:")) != EOF) {
switch (opt) {
case 'B':
@ -215,6 +235,9 @@ int main(int argc, char **argv)
case 'o':
opath = optarg;
break;
case 'S':
synth_flag = 1;
break;
case 's':
start = optarg;
break;
@ -224,6 +247,9 @@ int main(int argc, char **argv)
case 'v':
verbose_flag = 1;
break;
case 'W':
process_warning_switch(optarg);
break;
case '?':
default:
return 1;
@ -288,6 +314,9 @@ int main(int argc, char **argv)
/*
* $Log: iverilog.c,v $
* Revision 1.9 2000/05/03 22:14:31 steve
* More features of ivl available through iverilog.
*
* Revision 1.8 2000/05/01 23:55:22 steve
* Better inc and lib paths for iverilog.
*

40
iverilog.man
View File

@ -4,7 +4,7 @@ iverilog - Icarus Verilog compiler
.SH SYNOPSIS
.B iverilog
[-Dmacro[=defn]] [-E] [-fflag=value] [-Iincludepath] [-mmodule] [-ooutputfilename] [-stopmodule] [-ttype] [-v] sourcefile[s]
[-ESv] [-Dmacro[=defn]] [-fflag=value] [-Iincludepath] [-mmodule] [-ooutputfilename] [-s topmodule] [-ttype] [-Wclass] sourcefile[s]
.SH DESCRIPTION
.PP
@ -18,6 +18,13 @@ types are added as code generators are implemented.
.l
\fIiverilog\fP accepts the following options:
.TP 8
.B -B\fIbase\fP
The \fIiverilog\fP program uses external programs to preprocess and
compile the verilog source. Normally, the path used to locate these
tools is built into the \fIiverilog\fP program. However, the \fB-B\fP
switch allows the user to select a different set of programs. The path
given is used to locate \fIivlpp\fP, \fIivl\fP and the VPI modules.
.TP 8
.B -D\fImacro\fP
Defines macro \fImacro\fP with the string `1' as its definition. (NOT IMPLEMENTED)
.TP 8
@ -48,16 +55,33 @@ simulation. (NOT IMPLEMENTED)
Place output in the file \fIfilename\fP. If no output file name is
specified, \fIiverilog\fP uses the default name \fBa.out\fP.
.TP 8
.B -S
Synthesize. Normally, if the target can accept behavioral
descriptions, the compiler will leave processes in behavioral
form. The \fB-S\fP switch causes the compiler to perform synthesis
even if it is not necessary for the target. If the target type is a
netlist format, the \fB-S\fP switch is unnecessary and has no effect.
.TP 8
.B -s \fItopmodule\fP
Specify the top level module to elaborate. Icarus Verilog will by default
choose the only module that has no ports. However, this simplistic
heuristic is often not sufficient, and sometimes not what is wanted
anyhow.
.TP 8
.B -t\fItarget\fP
Use this switch to specify the target output format. See the
\fBTARGETS\fP section below for a list of valid output formats.
.TP 8
.B -v
Turn on verbose messages. This will print the command lines that are
executed to perform the actual compilation, along with version
information from the various components.
.TP 8
.B -W\fIclass\fP
Turn on different classes of warnings. See the \fBWARNING TYPES\fP
section below for desctriptions of the different warning groups. If
multiple \fB-W\fP switches are used, the warning set is the union of
all the requested classes.
.SH TARGETS
@ -81,6 +105,20 @@ devices in FPGAs or other programmable devices. The Icarus Verilog XNF
code generator can generate complete designs or XNF macros that can be
imported into larger designs by other tools.
.SH "WARNING TYPES"
These are the types of warnings that can be selected by the \fB-W\fP
switch.
.TP 8
.B all
This enables all supported warning categories.
.TP 8
.B implicit
This enables warnings for creation of implicit declarations. For
example, if a scaler wire X is used but not declared in the Verilog
source, this will print a warning at its first use.
.SH EXAMPLES
These examples assume that you have a Verilog source file called hello.v in
the current directory

7
main.cc
View File

@ -19,7 +19,7 @@ const char COPYRIGHT[] =
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT) && !defined(macintosh)
#ident "$Id: main.cc,v 1.31 2000/04/12 20:02:53 steve Exp $"
#ident "$Id: main.cc,v 1.32 2000/05/03 22:14:31 steve Exp $"
#endif
const char NOTICE[] =
@ -130,7 +130,7 @@ int main(int argc, char*argv[])
flags["VPI_MODULE_LIST"] = "system";
while ((opt = getopt(argc, argv, "F:f:hm:N:o:P:s:t:v")) != EOF) switch (opt) {
while ((opt = getopt(argc, argv, "F:f:hm:N:o:P:s:t:vW:")) != EOF) switch (opt) {
case 'F': {
net_func tmp = name_to_net_func(optarg);
if (tmp == 0) {
@ -305,6 +305,9 @@ int main(int argc, char*argv[])
/*
* $Log: main.cc,v $
* Revision 1.32 2000/05/03 22:14:31 steve
* More features of ivl available through iverilog.
*
* Revision 1.31 2000/04/12 20:02:53 steve
* Finally remove the NetNEvent and NetPEvent classes,
* Get synthesis working with the NetEvWait class,