iverilog man page.

Makefile.in

@@ -18,12 +18,12 @@
 #    59 Temple Place - Suite 330
 #    Boston, MA 02111-1307, USA
 #
-#ident "$Id: Makefile.in,v 1.46 2000/04/21 06:41:02 steve Exp $"
+#ident "$Id: Makefile.in,v 1.47 2000/04/26 20:53:21 steve Exp $"
 #
 #
 SHELL = /bin/sh
 
-VERSION = 0.2PRE
+VERSION = 0.3PRE
 
 prefix = @prefix@
 exec_prefix = @exec_prefix@
@@ -102,9 +102,6 @@ verilog: $(srcdir)/verilog.sh
 ivl: $O
 	$(CXX) $(CXXFLAGS) -o ivl $O
 
-gverilog: gverilog.c
-	$(CC) $(CPPFLAGS) -o gverilog -DLIBDIR='"@libdir@"' -DINCDIR='"@includedir@"' gverilog.c
-
 iverilog: iverilog.c
 	$(CC) $(CPPFLAGS) -o iverilog -DIVL_ROOT='"@libdir@/ivl"' iverilog.c
 
@@ -131,7 +128,7 @@ lexor_keyword.cc: lexor_keyword.gperf
 	gperf -o -i 7 -C -k 1-3,$$ -L ANSI-C -H keyword_hash -N check_identifier -t lexor_keyword.gperf > lexor_keyword.cc
 
 
-install: all installdirs $(bindir)/verilog $(bindir)/gverilog $(bindir)/iverilog $(libdir)/ivl/ivl $(mandir)/man1/verilog.1
+install: all installdirs $(bindir)/verilog $(bindir)/iverilog $(libdir)/ivl/ivl $(mandir)/man1/verilog.1 $(mandir)/man1/iverilog.1
 	cd vpi ; $(MAKE) install
 	cd vvm ; $(MAKE) install
 	cd ivlpp ; $(MAKE) install
@@ -139,9 +136,6 @@ install: all installdirs $(bindir)/verilog $(bindir)/gverilog $(bindir)/iverilog
 $(bindir)/verilog: ./verilog
 	$(INSTALL_SCRIPT) ./verilog $(bindir)/verilog
 
-$(bindir)/gverilog: ./gverilog
-	$(INSTALL_PROGRAM) ./gverilog $(bindir)/gverilog
-
 $(bindir)/iverilog: ./iverilog
 	$(INSTALL_PROGRAM) ./iverilog $(bindir)/iverilog
 
@@ -152,6 +146,9 @@ $(libdir)/ivl/ivl: ./ivl
 $(mandir)/man1/verilog.1: $(srcdir)/verilog.1
 	$(INSTALL_DATA) $(srcdir)/verilog.1 $(mandir)/man1/verilog.1
 
+$(mandir)/man1/iverilog.1: $(srcdir)/iverilog.man
+	$(INSTALL_DATA) $(srcdir)/iverilog.man $(mandir)/man1/iverilog.1
+
 installdirs: mkinstalldirs
 	$(srcdir)/mkinstalldirs $(bindir) $(libdir)/ivl $(mandir)/man1
 
@@ -161,6 +158,7 @@ uninstall:
 	rm -f $(bindir)/gverilog
 	rm -f $(bindir)/iverilog
 	rm -f $(mandir)/man1/verilog.1
+	rm -f $(mandir)/man1/iverilog.1
 	cd vpi ; $(MAKE) uninstall
 	cd vvm ; $(MAKE) uninstall
 	cd ivlpp ; $(MAKE) uninstall

iverilog.man

@@ -0,0 +1,107 @@
+.TH iverilog 1 "April, 2000" Version 19990913
+.SH NAME
+iverilog - Icarus Verilog compiler
+
+.SH SYNOPSIS
+.B iverilog
+[-Dmacro[=defn]] [-E] [-Iincludepath] [-mmodule] [-ooutputfilename] [-stopmodule] [-ttype] [-v] sourcefile[s]
+
+.SH DESCRIPTION
+.PP
+\fIiverilog\fP is a compiler that translates Verilog source code into
+executable programs for simulation, or other netlist formats for
+further processing. The currenty supported targets are \fIvvm\fP (for
+executable simulation) and \fIxnf\fP for synthesis. Other target
+types are added as code generators are implemented.
+
+.SH OPTIONS
+.l
+\fIiverilog\fP accepts the following options:
+.TP 8
+.B -D\fImacro\fP
+Defines macro \fImacro\fP with the string `1' as its definition. (NOT IMPLEMENTED)
+.TP 8
+.B -D\fImacro=defn\fP
+Defines macro \fImacro\fP as \fIdefn\fP. (NOT IMPLEMENTED)
+.TP 8
+.B -E
+Preprocess the Verilog source, but do not compile it. The output file
+is the Verilog input, but with file inclusions and macro references
+expanded and removed. This is useful, for example, to preprocess
+verilog source for use by other compilers.
+.TP 8
+.B -I\fIincludepath\fP 
+Append path \fIincludepath\fP to list of paths searched for Verilog
+include files. (NOT IMPLEMENTED)
+.TP 8
+.B -m\fImodule\fP
+Add this module to the list of VPI modules to be loaded by the
+simulation. (NOT IMPLEMENTED)
+.TP 8
+.B -o \fIfilename\fP
+Place output in the file \fIfilename\fP. If no output file name is
+specified, \fIiverilog\fP uses the default name \fBa.out\fP.
+.TP 8
+.B -s \fItopmodule\fP
+Specify the top level module to elaborate. Icarus Verilog will by default
+choose the only module that has no ports. However, this simplistic
+heuristic is often not sufficient, and sometimes not what is wanted
+anyhow.
+.TP 8
+.B -v
+Turn on verbose messages. This will print the command lines that are
+executed to perform the actual compilation, along with version
+information from the various components.
+
+.SH TARGETS
+
+The Icarus Verilog compiler supports a variety of targets, for
+different purposes, and the \fB-t\fP flag is used to select the
+desired target.
+
+.TP 8
+.B null
+The null target causes no code to be generated. It is useful for
+checking the syntax of the Verilog source.
+.TP 8
+.B vvm
+This is the default. The target is an executable program that uses the
+vvm simulation runtime. The compiler actually generates C++ code, then
+compiles and links that code to make the output executable.
+.TP 8
+.B xnf
+This is the Xilinx Netlist Format used by many tools for placing
+devices in FPGAs or other programmable devices. The Icarus Verilog XNF
+code generator can generate complete designs or XNF macros that can be
+imported into larger designs by other tools.
+
+.SH EXAMPLES 
+These examples assume that you have a Verilog source file called hello.v in
+the current directory
+
+To compile hello.v to an executable file called a.out:
+
+	verilog hello.v
+
+To compile hello.v to an executable file called hello:
+
+	verilog -o hello hello.v
+
+To compile hello.v to a file in XNF-format called hello.xnf
+
+	verilog -txnf -ohello.xnf hello.v
+
+
+.SH "AUTHOR"
+.nf
+Steve Williams (steve@icarus.com)
+
+.SH SEE ALSO
+.BR "<http://www.icarus.com/eda/verilog/>"
+
+.SH COPYRIGHT
+.nf
+Copyright \(co  2000 Stephen Williams
+
+This document can be freely redistributed according to the terms of the 
+GNU General Public License version 2.0