Normally there is at most one signal attached to a vvp functor, but
due to port collapsing, there can be more than one. If these signals
are array words, we need to trigger vpi callbacks on all the associated
arrays when the functor value changes.
(cherry picked from commit ac87138c44)
Currently we only issue a warning if a parameter override references
a parameter that doesn't exist, so do the same in this case.
(cherry picked from commit 42422d9940)
If there is a syntax error in the source code, pform_makegate may be
passed a null list of port connections. The error is already reported,
so we just need to ignore it.
(cherry picked from commit 8a5cbd4415)
This was already supported in command files, using the '-v' flag.
'-v' is already in use on the command line, so use '-l' instead,
and make that an alias for '-v' in command files.
(cherry picked from commit 7ddc514518)
(partial backport of commit d44c814bab)
Net arrays can be handled by nets directly, instead of creating
.alias records. But keep support for .alias records in vvp. to
maintain backwards compatibility.
Replace explicit comparisons against generation_flag with calls to
the gn_system_verilog helper function, both for code clarity and
to fix a couple of bugs. Also simplify the implementation of the
function, as we already rely on the generation_flag enumeration
being an ordered list.
(cherry picked from commit 3c9b39846c)
An out-of-range constant bit select on the LHS of an assignment was being
treated as an error, whereas an out-of range constant part select would
only result in a warning. In any other context, either case would result
in a warning, so convert the error to a warning.
In addition, all warnings for out-of-range or undefined constant bit/part
selects should be controlled by -Wselect-range.
(cherry picked from commit b51e58fa9d)
When emitting a design, all scopes must be emitted before emitting any
top level task/function/method definitions, otherwise hierarchical
references can't always be resolved.
(cherry picked from commit 2bc42fc6e2)
The calculation of the required multiplexer width was incorrect for
the corner case of a single guard value of zero.
(cherry picked from commit 27213f2af8)
SystemVerilog allows tasks, functions, and classes to be defined at the
root level or inside packages, so we can't rely on an enclosing module
being present to provide the timescale.
(cherry picked from commit 7bed181f68)
This just enables the compiler to parse path declarations that
contain part selects. As for bit selects, the part select is
discarded, and if elaboration of specify blocks is enabled,
the path declaration will be applied to the entire vector. If
elaboration is enabled, a warning message will now be output
when a bit or part select is discarded.
(cherry picked from commit ad87704809)
This does a better job of setting the intermediate expression types
and widths when calculating the canonical index into a packed array.
It still doesn't properly handle out-of-bound indices (br953).
(cherry picked from commit 7f612270b3)
The existing support for ``, `", and `\`" did not work in nested macro
definitions. Note that the new implementation only detects and replaces
these sequences inside the macro text (as required by the IEEE standard),
whereas the old implementation would detect and replace them anywhere in
the source files.
(cherry picked from commit 332170d36b)
The implementation of vvp_fun_part_pv::recv_vec4_pv was incorrect, and
propagated the incoming widths rather than the stored widths.
(cherry picked from commit 0c66116f51)
Martin Whitaker
Cary R
Stephen Williams
Henry Wong
Maciej Suminski