9c99b002ba
Resize vectors to mismatched ports
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It is legal in Verilog to bind expressions to ports that do not
match the port width. Icarus Verilog needs to create the necessary
part selects to get the connections right.
Signed-off-by: Stephen Williams <steve@icarus.com>
2007-09-09 21:14:52 -07:00
d43cda3def
Add port checks for primitives.
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This patch adds functionality to verify that primitives are given
an appropriate number of ports. For multiple output gates (but,
not, pulldown, pullup) it also reports that Icarus currently does
not support multiple outputs when more than one is given.
2007-09-06 18:50:02 -07:00
7c852aa075
Add cmos/rcmos primitives.
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This patch adds the cmos and rcmos primitives.
2007-09-06 18:46:22 -07:00
7bf4b64c0a
Check that logic gates are not given null ports.
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Logic gates do not handle null ports so check for this and
issue an error message when it happens.
2007-09-04 16:13:46 -07:00
4f6b47b345
Check that functions do not call invalid statements.
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This patch adds checks to verify that functions do not invoke
statements that are invalid for them (#, @, wait, enable/call
tasks and non blocking assignment). For reference see section
10.3.4 of 1364-2001.
2007-08-30 20:41:45 -07:00
845e74c30e
Evaluate parameter expressions losslessly
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Make sure parameter expressions are evaluated losslessly, as if
the l-value is unsigned and thus virtually infinite.
2007-06-27 22:05:36 -07:00
396ffd1cdd
Add support for conditional generate. In the process, fix bugs
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related to generate used multiple times by multiple scopes causing
spurious generation results.
Signed-off-by: Stephen Williams <steve@icarus.com>
2007-06-21 19:04:48 -07:00
b631268f56
Error resiliency (ldoolitt)
2007-06-05 21:35:51 +00:00
129a064e1a
Handle bit/part select of array words in nets.
2007-06-04 02:19:07 +00:00
c7d97f4146
Properly evaluate scope path expressions.
2007-06-02 03:42:12 +00:00
ddd36ecb6c
Rework the heirarchical identifier parse syntax and pform
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to handle more general combinations of heirarch and bit selects.
2007-05-24 04:07:11 +00:00
36471e9f96
Properly ignore unsupported ifnone.
2007-04-16 01:10:07 +00:00
79fdb2b243
Attach line number information to task calls.
2007-04-15 20:45:40 +00:00
f621448ced
Parse edge sensitive paths without edge specifier.
2007-04-13 02:34:35 +00:00
af913e7eb1
Allow implicit wires in assign l-value.
2007-04-05 03:09:50 +00:00
bd1b00ca29
Improve port mismatch error message.
2007-04-01 23:01:10 +00:00
611d2c81b3
Spelling fixes from Larry
2007-03-22 16:08:14 +00:00
d9efe3312e
Limit the calculated widths of constants.
2007-03-08 05:30:02 +00:00
e6fa72c318
Handle processes within generate loops.
2007-03-05 05:59:10 +00:00
606751dbfd
Check that path source/destination are ports.
2007-03-03 05:56:55 +00:00
fc9a90c9e0
Add support for edge sensitive spec paths.
2007-03-02 06:13:22 +00:00
243cf94165
Add support for conditional specify delay paths.
2007-03-01 06:19:38 +00:00
c1c2381261
Parse all specify paths to pform.
2007-02-12 01:52:21 +00:00
a623502ece
More generous handling of errors in blocks.
2007-02-01 05:52:24 +00:00
f77d803aeb
Clean up elaboration of for-loop increment expression.
2007-01-21 04:26:36 +00:00
ca9da51a79
Precalculate constant power expressions, and constant function arguments.
2007-01-19 05:42:40 +00:00
91d84e7dc7
Major rework of array handling. Memories are replaced with the
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more general concept of arrays. The NetMemory and NetEMemory
classes are removed from the ivl core program, and the IVL_LPM_RAM
lpm type is removed from the ivl_target API.
2007-01-16 05:44:14 +00:00
2c7d2effd1
Fix an uninitialized variable warning.
2006-12-09 01:59:35 +00:00
2eeea7003e
@* without inputs is an error.
2006-12-08 04:09:41 +00:00
48029ed8e5
Fix crash handling constant true conditional.
2006-11-27 02:01:07 +00:00
94f07d16e3
Fix compile time eval of condition expresion to do reduction OR of vectors.
2006-11-26 07:10:30 +00:00
041091cfac
Fix nexus widths for direct link assign and ternary nets.
2006-11-26 06:29:16 +00:00
c339dc4bbc
Remove last bits of relax_width methods, and use test_width
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to calculate the width of an r-value expression that may
contain unsized numbers.
2006-11-04 06:19:24 +00:00
2302693201
Expression widths with unsized literals are pseudo-infinite width.
2006-10-30 05:44:49 +00:00
4af28e2b77
no-specify turns of specparam elaboration.
2006-10-03 15:33:49 +00:00
69cd007a71
Support real valued specify delays, properly scaled.
2006-10-03 05:06:00 +00:00
d6be82f748
Support selective control of specify and xtypes features.
2006-09-28 04:35:18 +00:00
b658a3b41f
Missing PSpec.cc file.
2006-09-26 19:48:40 +00:00
0edb5a7547
Basic support for specify timing.
2006-09-23 04:57:19 +00:00
0e2c6544b9
Proper error message when logic array pi count is bad.
2006-09-22 22:14:27 +00:00
fc0695beb6
Handle 64bit delay constants.
2006-08-08 05:11:37 +00:00
71faebd6df
Make elaborate_expr methods aware of the width that the context
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requires of it. In the process, fix sizing of the width of unary
minus is context determined sizes.
2006-06-02 04:48:49 +00:00
a8b86ea3bb
More explicit datatype setup.
2006-05-01 20:47:58 +00:00
0c9fb766b6
Get the data type of part select results right.
2006-04-30 05:17:48 +00:00
4493e3f928
Chop down assign r-values that elaborate too wide.
2006-04-26 04:43:50 +00:00
f001d0001a
Add support for generate loops w/ wires and gates.
2006-04-10 00:37:42 +00:00
e8efa6df53
Fix instance arrays indexed by overridden parameters.
2006-03-30 01:49:07 +00:00
368c27c9e4
Handle complex net node delays.
2006-01-03 05:22:14 +00:00
58f182a159
Node delays can be more general expressions in structural contexts.
2006-01-02 05:33:19 +00:00
0e044d6684
More precise about r-value width of constants.
2005-11-26 00:35:42 +00:00
Stephen Williams
Cary R
steve