7eb0efd424
Add basic support for vpiBit
2020-05-31 00:27:15 -07:00
19d63f0c96
A VPI by index will only work for a reg or a net
2020-05-18 22:57:18 -07:00
0a06ecb203
Update vpi_mcd_close() to return the correct value
2020-05-16 19:19:45 -07:00
fc7f0739d3
When a FD is passed to vpi_mcd_(v)print return EOF since this is an error
2020-05-16 19:19:30 -07:00
514ddade39
Add missing include for malloc()
2020-05-11 19:00:38 +02:00
cf44f05cd3
Fix GitHub issue #324 - replace __CYGWIN32__ with __CYGWIN__.
...
__CYGWIN32__ is not defined when building with the 64-bit Cygwin
toolchain. According to the Cygwin FAQ, __CYGWIN__ has been defined
since 1998, so this should still work for users on 32-bit systems.
2020-05-10 14:06:53 +01:00
cf193b3055
Cleanup vpiClassTypespec when running valgrind
2020-05-09 23:04:37 -07:00
58eb202376
Update find_scope and vpi_handle_by_name to work with escaped identifiers
2020-05-02 19:47:56 -07:00
11001f58d5
Thoroughly fix parallel installation issues
...
In PR #300 , @xdch47 pointed out a stable way to fix parallel
installation problems.
This fix applied the method, thanks!
Signed-off-by: Huang Rui <vowstar@gmail.com>
2020-02-12 22:42:04 +08:00
0602ef46c6
[17/20]driver/Makefile.in:fix install timestamp check
...
Fix tgt-fpga/Makefile.in vvp/Makefile.in doc
Fix bug: https://bugs.gentoo.org/705412
Fix bug: https://github.com/gentoo/gentoo/pull/14096
Related: https://github.com/steveicarus/iverilog/pull/294
Signed-off-by: Huang Rui <vowstar@gmail.com>
2020-02-12 22:08:40 +08:00
081fe1c816
[1/20]vvp/Makefile.in:fix install timestamp check
...
Fix bug: https://bugs.gentoo.org/705412
Fix bug: https://github.com/gentoo/gentoo/pull/14096
Related: https://github.com/steveicarus/iverilog/pull/294
Signed-off-by: Huang Rui <vowstar@gmail.com>
2020-02-12 22:08:40 +08:00
398d0cb82f
Fix bad bounds check in for loop
2020-02-05 08:05:50 -08:00
b91d5d1a82
vvp: recognise signed logic types when parsing class properties.
2019-12-23 09:48:07 +00:00
7f95abc6ab
Make a pass at implementing cbAtEndOfSimTime.
...
In Icarus Verilog, AtEndOfSimTime is practically the same as
cbReadWriteSync, since the latter is after non-blocking events
in Icarus Verilog.
2019-11-25 17:57:10 -08:00
351a4e5f5e
Improve vvp handling of excessively large shift distances.
2019-11-16 12:11:49 +00:00
0a4cae2644
Fix vvp %shift instructions to treat right operand as unsigned.
...
1364-2005 section 5.1.12 says "The right operand is always treated
as an unsigned number".
This fixes GitHub issue #283 .
2019-11-15 21:24:47 +00:00
d1d409fd88
Add version check for VPI routines callback.
2019-10-30 20:16:30 +00:00
9fb952ed72
Use functions instead of macros for VPI routine redirection in Windows.
2019-10-27 09:06:55 +00:00
3f1253039a
Only use VPI routine jump table in Windows.
2019-10-25 10:07:57 +01:00
79d3a21b65
Minor code tidy-up.
2019-10-22 21:52:52 +01:00
e6b0396e6f
Makefile fixes.
2019-10-22 16:51:14 +01:00
a59b183bd1
Allow VPI modules to be loaded by multiple clients under Windows.
...
The old scheme of linking the VPI modules with the vvp exports meant they
did not work when loaded by the compiler. Instead, let each client create
a jump table for the VPI routines and pass that to each VPI module as it
is loaded.
2019-10-22 16:00:13 +01:00
0abf91ca4e
Make vvp exit with FAILURE if $fatal is used to exit the simulation.
2019-10-14 14:11:50 -07:00
ea4e41207c
Update cppcheck standards that are checked
2019-09-30 22:14:15 -07:00
ba82ef463e
Fix some always_* issues
2019-09-29 16:59:59 -07:00
1aa22735ce
Add new %cast/vec2/dar and %cast/vec4/dar instructions to vvp.
2019-09-11 21:56:27 +01:00
74ff44314e
Add new %cast/vec4/str instruction to vvp.
2019-09-11 21:56:09 +01:00
3bdb50da29
Schedule UDP initial 0/1 assignments to occur during time 0.
...
This allows any always processes that are sensitive to the UDP output
to start first. This fixes a time 0 race that was found in a Lattice
Semiconductor simulation library (reported on iverilog-devel).
If the initial value is 'x', propagate the value to the UDP output
before the start of simulation, to avoid unwanted update events on
the z -> x transition on downstream nets.
2019-08-09 21:00:10 +01:00
866cc46915
Fix for GitHub issue #256 - don't use V as Makefile variable name.
...
Some build systems override V on the make command line, wrongly assuming
it is the automake verbose option.
2019-08-02 10:27:40 +01:00
c383d2048c
Fix initialisation of vvp symbol table values.
...
In 64-bit Windows, an unsigned long is 32 bits, so initialising the num
member of the union did not properly initialise the ptr member. The num
member isn't actually needed, so eliminate it.
2019-08-01 12:34:47 +01:00
8402696676
Fix VPI interface to APV objects.
...
- type is vpiPartSelect, not vpiMemoryWord
- left/right range is for part, not full word
- index is not valid for a part select
The user will now get a sensible error message if they pass part of an
array word to $dumpvars (GitHub issue #230 ).
2019-07-25 08:58:00 +01:00
8cd8bed22e
Fix GitHub issue #243 - support arbitrary width static bit arrays in vvp.
2019-07-24 09:15:44 +01:00
5bb6c7f53a
Fix makefile rules for header files generated by bison.
...
bison 3.4.1 writes the header file before the c++ file. Our makefile
rules make the header files depend on the c++ files, so we need to
fix the timestamps accordingly.
2019-06-02 18:50:18 +01:00
c3575d379b
Merge branch 'master' into cross_compile
2019-03-24 10:27:33 -07:00
51a13e883a
Fix for GitHub issue 235: segfault when calling vpi_handle_by_name().
...
When vpi_handle_by_name() iterates over the VPI objects in a scope, handle
the case that vpi_get_str() returns a null value. This currently occurs if
the scope contains an enum type definition, as vpi_get_str() is not
implemented for __vpiEnumTypespec.
2019-03-23 17:21:40 +00:00
c3d5b23ac4
Fix some Windows build issues.
2019-03-22 08:08:29 -07:00
2ff6af254b
Use LLONG_MIN instead of LONG_LONG_MIN.
...
GCC 8 no longer defines LONG_LONG_MIN. We already assume a C99 compliant
compiler in other places.
2019-01-26 16:47:28 +00:00
6887c31d8c
Refactor vpi module path code.
...
Also restore the original behaviour of the '-M -' option, although it's
probably not needed now we add the default path last.
2018-10-29 20:33:52 +00:00
a1ad6d4b51
Support IVERILOG_VPI_MODULE_PATH environment variable
2018-10-28 12:44:09 -07:00
a638d1eed0
Check for too many paths specified and fix path priority so paths specified on command line supersede built-in paths
2018-10-28 12:43:40 -07:00
5aae9ea770
Fix bit width when converting real value to binary/hex string in VPI.
2018-10-07 17:17:33 +01:00
3e25b04685
SIGHUP is not available in Windows.
2018-10-06 21:07:13 +01:00
f1608e163f
Fix implicit fallthrough warnings when building with recent GCC.
2018-10-06 20:15:42 +01:00
542fe2cf77
Enable checks for VPI const-correctness.
...
Note we only want these enabled when building the compiler and runtime
binaries. If we included the ICARUS_VPI_CONST definition in the global
CPP_FLAGS, that would propagate to the flags used by iverilog-vpi, so
would affect compilation of user VPI code.
2018-10-06 11:48:19 +01:00
603ff303f5
Cleanly terminate vvp on SIGHUP or SIGTERM (GitHub issue #203 ).
2018-09-29 23:25:04 +01:00
11c826216a
Fix for GitHub issue #198 - support octal display for thread variables.
2018-06-12 22:58:07 +01:00
7ad5b59a6f
Fix for GitHub issue #199 : handle signed division overflow.
...
When performing a signed division or modulus operation using native
arithmetic, trap the special case that the numerator is the minimum
integer value and the denominator is -1, as this gives an undefined
result in C++.
2018-06-12 21:59:58 +01:00
6e49ab10ec
Further fix for br1029.
...
The code in vpi_callback.cc is replicated in vpi_vthr_vector.cc,
so we have to replicate the fix. This should really be factored
out.
2018-05-14 22:14:51 +01:00
5a4e99b0e8
Fix br1029 - correct rounding when vpi_get_value converts real to integer string.
2018-05-12 23:49:11 +01:00
5cfb7d68ae
Add support for rtran switches in vvp.
2018-02-23 22:30:32 +00:00
36eef5154f
Implement supply->strong strength reduction for non-resistive switches.
...
As specified in 1364-2005 section 7.11.
2018-02-23 22:07:59 +00:00
24a4ec3bb2
Hide the always_comb/latch TO event by not attaching it to a scope.
2018-01-01 21:19:58 -08:00
0caa109174
Merge pull request #181 from phire/portinfo_grammar
...
vvp grammar: .port_info statements should require/generate semicolons.
2017-12-18 10:04:42 -08:00
d01e5accc0
vpp: Require semicolon after .port_info statements
...
Optional until 12.0
2017-12-17 00:06:09 +13:00
db1ea05452
Fix #0 to trigger in the inactive region and add a trigger for always_comb/latch
2017-12-03 20:17:42 -08:00
3fc9ad2db0
Add support for the wild compare operators ==? and !=?
2017-11-17 19:32:50 -08:00
f03033e612
Update flex destroy routines to work for version 2.6 and greater
2017-11-16 19:11:50 -08:00
ad83a135e5
Fix assertion failure in vvp wide functor.
...
If the functor output is read before any values have propagated to
the functor inputs, the internal storage won't have been initialised.
2017-11-08 20:35:18 +00:00
c622d372f9
Fix for GitHub issue #169 : nets can get given wrong scope in VPI.
...
In vvp, the __vpiSignal object holds a pointer to the scope containing
the signal. This was getting set to the current scope when the net was
finally resolved, rather than to the scope where the net was declared.
2017-11-07 18:48:48 +00:00
d9478bd837
Update cppcheck waiver files
2017-10-23 00:21:51 -07:00
5ca058bfb5
Add support for darray initialisation from another darray.
...
Fixes GitHub issue #164 .
2017-10-08 17:51:33 +01:00
e315cafa01
Fix for GitHub issue #165 : assertion failure on thread join.
...
If a thread becomes detached due to a join_any statement, that
thread must not attempt to join its parent, even if the parent
is waiting on a subsequent join statement.
2017-10-07 16:41:26 +01:00
a1a7f5deff
Fix error in last commit.
2017-09-17 19:58:13 +01:00
0bed890bc6
Fix use after free bug in vvp when a task or function is disabled.
...
Use test_joinable() and do_join() to ensure everything gets cleaned
up before the thread is reaped. This should fix br1016, br1017, and
br1018.
2017-09-17 19:48:54 +01:00
ac87138c44
Fix for br1019 - allow multiple array words to be attached to a vpi callback.
...
Normally there is at most one signal attached to a vvp functor, but
due to port collapsing, there can be more than one. If these signals
are array words, we need to trigger vpi callbacks on all the associated
arrays when the functor value changes.
2017-08-12 12:23:43 +01:00
62e0f59b07
No need for class in previous patch
2017-06-19 21:26:24 -07:00
10ef0eb109
Fix class versus struct warning in clang
2017-06-19 21:26:16 -07:00
e2be64558b
Ensure value passed to named event via vpi_put_value() is initialised.
...
The __vpiNamedEvent::vpi_put_value() function ignores the value, but
intermediate code looks at it.
2017-06-15 09:11:11 +01:00
3de7c234f7
Implement vpi_put_value() for named events (GitHub issue #158 ).
2017-06-15 08:47:29 +01:00
c79df7c44b
fix failing VPI callbacks the vpip_cur_task was left dangling
2017-01-01 17:44:54 -08:00
f48b0e3434
Allows compiling for Windows (32 or 64 bits) under Linux.
2016-12-11 03:40:35 +02:00
2127680e49
Fixed cross-compile using mingw 64 bit under Windows 10 Linux subsystem (Ubunto 14.04)
...
Should work with true Ubuntu 14.04 as-is.
2016-12-08 00:11:22 +02:00
0fdf29e099
Fix for GitHub issue #117 - delays in VPI simulation time callbacks.
...
Change cbReadWriteSynch and cbReadOnlySynch to interpret the passed
time value as a relative delay, not an absolute time. This matches
the behaviour of other simulators.
2016-09-25 20:43:58 +01:00
e56e52bc42
Merge branch 'master' of github.com:steveicarus/iverilog
2016-09-19 12:59:41 -07:00
f32b64f497
Fixed warnings about shifting a negative value
2016-09-19 12:54:15 -07:00
5853e32f82
Fix some cppcheck warning issues
2016-09-13 23:45:25 -07:00
d44c814bab
Remove .alias records from vvp generated code.
...
Net arrays can be handled by nets directly, instead of creating
.alias records.
2016-08-31 14:05:09 -07:00
a2fbdeff78
Add some pass by reference to vvp
2016-08-14 22:26:16 -07:00
ad5a7f7ca3
Update cppcheck vvp suppression file
2016-08-14 21:18:55 -07:00
d0e0776910
Make the base class match the derived classes regarding passing by reference
2016-08-14 21:18:44 -07:00
7bed181f68
Support timescales in design units that aren't inside a module.
...
SystemVerilog allows tasks, functions, and classes to be defined at the
root level or inside packages, so we can't rely on an enclosing module
being present to provide the timescale.
2016-07-22 22:48:20 +01:00
43cd693fe0
Put start events to proper queue.
2016-07-17 09:47:08 -07:00
9ad46044b4
Cleanup
2016-06-30 17:47:34 +02:00
8234f1845d
Fix for GitHub issue #106 - prevent VPI writes during read-only synch.
2016-06-09 21:27:20 +01:00
61c82d2cb0
Handle mixed continuous and non-blocking assignments to same vector.
...
SystemVerilog allows a mixture of procedural and continuous assignments
to be applied to different parts of the same vector. The previous attempt
to make this work for non-blocking assignments was flawed (see preceding
fix for vvp_fun_part_pv::recv_vec4_pv). Instead, handle this case by
converting the non-blocking assignment into a delayed force statement,
which matches the way mixed continuous and blocking assignments are
handled.
2016-05-10 22:16:40 +01:00
0c66116f51
Fix for GitHub issue #103 - vvp assertion failure on part select propagation.
...
The implementation of vvp_fun_part_pv::recv_vec4_pv was incorrect, and
propagated the incoming widths rather than the stored widths.
2016-05-10 21:59:21 +01:00
6e5ed73b09
Extended fix for GitHub issue #99 .
...
Most vvp functors need to support recv_vec4_pv. Any that are strength-aware
also need to support recv_vec8_pv. Note the simplifying assumption that is
documented in the base class recv_vec4_pv_ implementation.
2016-04-18 23:47:43 +01:00
b2f7d09f0d
Fix GitHub issue #99 - recv_vec4_pv not implemented for arithmetic functors.
...
Also initialise the stored operand values to 'bz instead of 'bx to get
the correct results when bits are not driven.
2016-04-04 22:29:54 +01:00
4521be4510
More spelling, comments only
2016-04-01 11:02:34 -07:00
89edf62206
Capitalize Verilog in a few places
2016-04-01 11:02:24 -07:00
0dcb46e4c4
Fix shadow warning.
2016-03-19 14:42:34 +00:00
54feb89bf5
For SystemVerilog, run variable initialization before main simulation starts.
2016-03-19 13:46:09 +00:00
78a49eacef
Merge branch 'master' of github.com:steveicarus/iverilog
2016-03-14 12:26:12 -07:00
1784488096
Spelling and whitespace
2016-03-14 12:25:50 -07:00
dc189fec8c
Added new vvp latch statement to README file.
2016-03-12 12:14:03 +00:00
99afea6946
Added support for LPM latches to vvp.
2016-03-12 09:04:51 +00:00
9cf1dcbae2
vvp: Corrected vvp_net_fun_t::recv_vec4_pv() (commit de968e18)
2016-03-07 09:54:28 +01:00
69b7c000d0
vvp: Implemented vvp_net_fun_t::recv_vec4_pv().
2016-03-07 09:54:28 +01:00
9a7f31c728
Functions that return strings pass the return value on the stack.
2016-03-01 15:38:28 -08:00
7d21891147
Fix space issues.
2016-02-28 22:09:39 -08:00
Cary R
Tim Pambor
Martin Whitaker
Huang Rui
Greg Steuck
Stephen Williams
Alex Forencich
Scott Mansell
Johann Klammer
Udi Finkelstein
Maciej Suminski
Yury Gribov
Michele Castellana
Larry Doolittle