In multi-dimensional packed arrays, allow variable indices in the outer
(prefix) dimensions, not just the final dimension. For example:
logic [3:0][3:0] a;
for (int i=0; i<4; i++)
a[i][3] = 1; // Previously error, now works
The fix checks if any packed prefix indices are non-constant. If so,
use collapse_array_exprs() to compute the bit offset as an expression
rather than requiring constant indices.
This removes an artificial restriction that had no justification in
the IEEE standard, as noted by maintainers in the GitHub issue.
Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
Per IEEE 1800-2017 6.5, variables can be written by one port, including
primitive gate outputs. The code incorrectly disallowed this with the
comment "Gates can never have variable output ports."
Changed elaborate_lnet/elaborate_bi_net calls for gate outputs to pass
true for var_allowed_in_sv, allowing variables as single-driver outputs.
Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
The tgt-sizer target now skips IVL_SCT_PACKAGE scopes (the SystemVerilog
$unit compilation unit scope) instead of erroring. This allows sizer to
work with -g2012 and other SystemVerilog modes.
Includes regression test: br_gh1170
Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
Modified grammar in parse.y to use identifier_name instead of IDENTIFIER
in function/task declaration rules and hierarchy_identifier rule. This
allows TYPE_IDENTIFIER tokens (which class names become after definition)
to be used as method names.
Changes:
- Function declaration rules (lines 1585, 1605, 1631)
- Task declaration rules (lines 2445, 2472, 2501)
- hierarchy_identifier member access (line 4471)
Includes regression test: br_gh670
Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
When $bits() is called with an undefined identifier, the compiler now
properly reports an error instead of silently returning 0.
The fix checks if the argument expression has type IVL_VT_NO_TYPE after
test_width() processing (indicating the identifier couldn't be resolved),
and triggers elaboration to produce a proper error message.
Includes regression test: br_gh1112
Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
Currently, when a constant bit/part select is found in the implicit
sensitivity list for an always_* construct, it is replaced by the
entire signal. If there is more than one bit/part select from the
same signal, that signal gets added to the list multiple times. This
breaks the algorithm used to detect duplicate events in the nodangle
functor, causing it to erroneously merge non-identical events in some
cases.
The proper fix is to support sensitivity at the bit/part level, as
required by IEEE 1800. But for now, just make sure we only include
the entire signal once, regardless of how many different bit/part
selects we find. Enhance the "sorry" message to report which signals
are contributing excessively to the process sensitivity.
Andrew Pullin
Cary R
Martin Whitaker