luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix #1170: Skip $unit scope in tgt-sizer 

The tgt-sizer target now skips IVL_SCT_PACKAGE scopes (the SystemVerilog
$unit compilation unit scope) instead of erroring. This allows sizer to
work with -g2012 and other SystemVerilog modes.

Includes regression test: br_gh1170

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
This commit is contained in:
Andrew Pullin 2026-01-23 11:08:47 -08:00
parent b6042215ff
commit d540260a20
4 changed files with 12 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
ivtest/ivltests/br_gh1170.v Normal file
View File

@ -0,0 +1,6 @@
// Test for GitHub issue #1170
// tgt-sizer should work with SystemVerilog 2012 ($unit scope)
module test;
logic [7:0] data;
assign data = 8'hAA;
endmodule

2
ivtest/perl-lib/RegressionList.pm
View File

@ -102,7 +102,7 @@ sub read_regression_list {
$args{$tname} = "";
}
if ($opt ne "std") {
$args{$tname} = $opt . $args{$tname};
$args{$tname} = $opt . ($args{$tname} ? " " . $args{$tname} : "");
}
$srcpath{$tname} = $fields[2];

1
ivtest/regress-synth.list
View File

@ -137,3 +137,4 @@ ssetclr2 normal ivltests
ssetclr3 normal ivltests
synth_if_no_else normal ivltests
ufuncsynth1 normal ivltests
br_gh1170 CO,-g2012,-tsizer ivltests

4
tgt-sizer/sizer.cc
View File

@ -92,6 +92,10 @@ int target_design(ivl_design_t des)
// multiple root scopes, we will give isolated numbers for
// each and keep then separate.
for (unsigned idx = 0 ; idx < nroots ; idx += 1) {
// Skip SystemVerilog $unit scope (compilation unit scope)
if (ivl_scope_type(roots[idx]) == IVL_SCT_PACKAGE) {
continue;
}
if (ivl_scope_type(roots[idx]) != IVL_SCT_MODULE) {
fprintf(stderr, "SIZER: The root scope %s must be a module.\n", ivl_scope_basename(roots[idx]));
sizer_errors += 1;