bdd0657140
Reject default task/function arguments when parsing traditional Verilog.
2015-06-21 09:05:39 +01:00
1d279798d8
Fix for br982 - detect and report missing output arguments in task calls.
2015-06-20 22:39:55 +01:00
0e66e9781a
Add support for non-constant default subroutine arguments.
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Input ports only at the moment. Output "sorry" message for other
port types.
2015-06-20 21:39:45 +01:00
b23faff27c
Just a few more spelling fixes
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Includes some user-visible messages
2015-06-17 08:09:34 -07:00
b242663cae
Support negedge flip-flops in synthesis and in vvp.
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Also extend the support for FF asynchronous set values to vvp and
fix the dff functor in vvp to correctly model asynchronous set/clr
behaviour.
2015-06-13 16:47:57 +01:00
d39c284055
Observe and propagate failures when synthesising lval concatenations.
2015-06-13 16:47:57 +01:00
6a73de0c43
Merge pull request #70 from orsonmmz/time
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Time expressions for vhdlpp
2015-06-08 16:17:40 -07:00
e0cdd71984
Minor cleanup and simplification of aset_value changes.
2015-06-08 21:20:49 +01:00
81e1735959
establish support for aset_value and reorder clauses so vlog95 doesn't fail anymore.
2015-06-08 20:34:50 +01:00
3fb65eb51a
single bit reset
2015-06-08 20:34:43 +01:00
3080f5730d
Better implementation of assignment lval concatenation synthesis.
2015-06-08 20:27:38 +01:00
29ddd5208f
vhdlpp: 'wait on' and 'wait until' statements.
2015-06-08 18:42:52 +02:00
4a31f36646
vhdlpp: Minor code cleaning.
2015-06-08 18:42:52 +02:00
1f1d47887e
vhdlpp: Visitor for Expression class.
2015-06-08 18:42:52 +02:00
80403d2ade
ivl: Disabled reg_flag for time type in SV.
2015-06-08 18:42:52 +02:00
cd3180d1c2
ivl: TIME_LITERAL added as a primary expression.
2015-06-08 18:42:52 +02:00
68f8007fc4
vhdlpp: 'wait for' statement.
2015-06-08 18:42:52 +02:00
d6ff1946f9
vhdlpp: Support for time expressions.
2015-06-08 18:42:52 +02:00
4068c172f4
Fix overzealous detection of duplicate net/variable declarations.
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As reported by Larry Doolittle on iverilog-devel.
2015-06-07 08:48:33 +01:00
9ac9f1c9f2
Merge branch 'master' of github.com:steveicarus/iverilog
2015-06-04 15:11:29 -07:00
2739f83702
Spelling fixes in C and C++ comments
2015-06-04 15:00:29 -07:00
7af3280215
Update cppcheck suppression file in VPI
2015-06-04 09:50:08 -07:00
05d591ccd6
Fix broken write to log files.
2015-06-03 14:32:04 -07:00
fbedf4ae22
Snapshot 2015-06-03
2015-06-03 11:16:07 -07:00
e6c6f6c81e
Use fwrite to write $display output, instead of fprintf
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This change makes it safe to write non-ascii characters, which
is an issue when the %u format is used.
2015-06-03 10:00:35 -07:00
33c651aa00
Spelling fixes in .txt files
2015-05-25 12:52:03 -07:00
358bb4d5d9
Merge branch 'master' of github.com:steveicarus/iverilog
2015-05-25 12:51:20 -07:00
d5b41853fd
Fix for br979 part 2 - handle blank lines in macro definition continuation.
2015-05-22 18:44:25 +01:00
0fc10e3e70
Fix for br979 part 1 - strip leading/trailing space from macro actual args.
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Although the IEEE standard doesn't explicitly state this is required,
the examples added in the SystemVerilog standard show that this is
expected.
Also add a preprocessor lexical rule to recognise `` inside a macro
definition when it is not immediately followed by an identifier.
2015-05-22 18:11:24 +01:00
ab688613cc
Fix for br978 - assertion involving addition of $ivlh_to_unsigned() result.
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$ivlh_to_unsigned, unlike $signed and $signed, can cause a reduction
in width. The shared PECallFunction::cast_to_width_ method did not
support this.
2015-05-22 00:05:39 +01:00
79042e38ad
Merge branch 'master' of github.com:steveicarus/iverilog
2015-05-21 10:05:37 -07:00
ced9759c65
Merge pull request #69 from orsonmmz/fixes
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Various fixes
2015-05-21 10:05:26 -07:00
8f22998447
Merge branch 'master' of github.com:steveicarus/iverilog
2015-05-21 09:58:36 -07:00
51d7237d52
vhdlpp: Display error message for undefined generic values.
2015-05-21 01:25:34 +02:00
7aab315ce5
vhdlpp: Allow assigning values to inout ports.
2015-05-20 17:30:07 +02:00
bc83d2914a
vhdlpp: Corrected an error message for attributes.
2015-05-20 14:23:57 +02:00
bb2e6782fa
Copy constructor for LineInfo.
2015-05-19 22:40:56 +02:00
9231ad51a4
vhdlpp: generics without a default value are set to 1'bx.
2015-05-19 22:40:56 +02:00
25458b8cc2
vhdlpp: inout direction for ports.
2015-05-19 22:40:56 +02:00
515ab40ffe
vhdlpp: Special handling for string type emission.
2015-05-19 22:40:56 +02:00
ddc204391e
vhdlpp: Add 'sub' prefix for subtypes while emitting packages.
2015-05-19 22:40:55 +02:00
a33bbecc98
vhdlpp: VTypeRange::write_to_stream uses to/downto depending on the range boundaries.
2015-05-19 22:40:55 +02:00
61ace52f31
Fix vlog95 target to not output data types in port declarations.
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This avoids variable redeclaration errors.
2015-05-18 23:16:53 +01:00
71b1546a7d
Fail gracefully when an unpacked struct is declared.
2015-05-17 21:59:05 +01:00
578a2543f7
Fix for br975 - assertion failure due to duplicate declaration of struct var.
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Added proper error handling for duplicate declarations of all variable
types.
2015-05-17 20:54:53 +01:00
a479bd6b16
Fix for br977 - preprocessor macros substitute text inside token.
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When replacing macro formal parameters, the preprocessor should not
replace matching strings that are not complete tokens. The test for
this was incorrect, and failed when a match was found at the start
of the replacement text.
2015-05-17 20:05:45 +01:00
c75498b1d4
Add -i (interactive) option to vvp.
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This forces <stdout> to be unbuffered. This is useful when using the
mintty terminal emulator in Windows (as used by MSYS2 and CygWin),
which identifies as a pipe, not a tty.
2015-05-16 00:39:03 +01:00
b6304129fa
Fix for GutHub issue #64 - vvp interrupt/continue in Windows.
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Windows implements the original UNIX semantics for signal(), which
means you have to re-establish the signal handler each time a signal
is caught.
2015-05-15 22:30:03 +01:00
50180ac4a6
Add clang support for travis
2015-05-13 21:35:21 +02:00
bb444b6178
Snapshot 2015-05-13
2015-05-13 10:21:19 -07:00
Martin Whitaker
Larry Doolittle
Stephen Williams
Johann Klammer
Maciej Suminski
Cary R
Tomasz Hemperek