08afbde08d
Update cppcheck suppression file for tgt-vlog.
2014-10-30 18:23:39 -07:00
7ab0824adf
Fix for br961 - function return type elaborated in wrong scope.
...
The return type of a function should be elaborated in the context of
the enclosing scope, not in the context of the function itself.
2014-10-30 21:09:17 +00:00
7fad4779c5
Add error recovery when elaboration of a type range fails.
...
If elaboration of the msb or lsb expression in the range of a vector
type specification failed (due to an error in the Verilog code being
compiled), an assertion failure was being triggered when the compiler
attempted to evaluate the expressions. Bypassing the evaluation (and
using a default value) should allow us to recover from the error.
2014-10-30 20:42:12 +00:00
3e9c14060f
lexor handles arbitrary length defines in the precompiled_defiles file.
2014-10-25 09:48:11 -07:00
006aef93d0
Fix a reference to an undefined element.
2014-10-23 16:56:13 -07:00
a63ca15735
Add support for putting a single delay from the VPI
2014-10-18 18:27:39 -07:00
d139142c29
Merge pull request #47 from orsonmmz/concat
...
Expression concatenation in VHDL
2014-10-18 15:13:50 -07:00
af85d44d9f
Add support for putting three and six delays from the VPI
2014-10-17 20:06:01 -07:00
c5e0507941
Fix the modpath edge and vpi_put_delay() code
...
The code to get the correct modpath delay for a given edge had the X and Z
entries swapped.
When putting a delay from the VPI the 2 delay to twelve delay mapping was
incorrect and the to/from X delays were also not being calculated correctly.
2014-10-17 19:42:55 -07:00
c55a013162
vhdlpp: Support for integer() function.
...
Note: I could not find any info about the integer() function, but it is
used in the VHDL standard packages (e.g. math_real, see:
http://www.csee.umbc.edu/portal/help/VHDL/packages/mathpack.vhd )
Real numbers are rounded, this is compatible with ModelSim behavior.
2014-10-17 14:53:59 +02:00
dfbca0b186
vhdlpp: Emit use_types in Architecture.
2014-10-17 14:13:06 +02:00
4a779f43bd
vhdlpp: Fix error message for 'right attribute.
2014-10-17 14:13:06 +02:00
97df6183a9
vhdlpp: Emit '-' std_logic value as 'x'.
...
Note: It is not a direct ("don't care" vs "unknown"), but I could not
find anything that suits better.
2014-10-17 14:13:06 +02:00
95faed8e9d
vhdlpp: Added basic support for concatenated expressions.
2014-10-15 10:51:21 +02:00
76aab15798
vhdlpp: Minor code cleaning.
2014-10-15 10:51:21 +02:00
e896f0c8e6
Remove some compile warnings in the vhdlpp code
2014-10-14 09:03:42 -07:00
f36bebf0e1
Remove some compile warnings.
2014-10-13 16:31:53 -07:00
3fd622e4eb
vlog95: Add support for emitting global tasks and functions
2014-10-13 09:51:55 -07:00
da4200c5bd
Update lz4 files to the latest from GTKWave
2014-10-13 09:44:57 -07:00
712f394224
Elaborate classes in packages.
2014-10-10 18:53:53 -07:00
d6685f40a1
Merge pull request #46 from orsonmmz/range
...
VHDL attributes: 'range, 'reverse_range, 'left & 'right
2014-10-10 17:23:59 -07:00
9ff9cbf4aa
vhdlpp: Smarter determining the direction in for loops.
2014-10-10 18:39:14 +02:00
a992f3ce7c
vhdlpp: Evaluation for 'left and 'right attributes.
2014-10-10 18:35:17 +02:00
1a4edcac48
vvp: Accepts continuous assignment for 2-state nets.
2014-10-10 16:16:46 +02:00
8cac72192f
vhdlpp: Fix array typedefs in packages.
2014-10-09 10:37:33 +02:00
7f6100be2a
vhdlpp: Emit VHDL 'integer' as SystemVerilog 'int'.
2014-10-09 10:29:14 +02:00
4b60d2737e
vhdlpp: Skip signed & unsigned in types dump in packages.
2014-10-09 10:28:35 +02:00
c7beef907d
vhdlpp: Support for 'range and 'reverse_range attributes.
2014-10-08 11:18:06 +02:00
44da7de651
vhdlpp: prange_t may have the direction determined automatically.
2014-10-08 10:26:37 +02:00
6887c82540
vhdlpp: Added ExpAttribute::write_to_stream().
2014-10-08 10:21:03 +02:00
1333bc54a2
vhdlpp: Support for 'left & 'right attributes.
2014-10-08 10:05:04 +02:00
fddb3ec129
vhdlpp: ForLoopStatement emits range boundaries expressions instead of evaluating them.
...
Unfortunately without evaluation it is not possible to warn against
degenerated loops, so it had to be removed.
2014-10-07 14:25:00 +02:00
bfafd175fa
Fix parse.y bad handling of file names in some situations.
...
The YYLLOC_DEFAULT() macro needs to get the .text value even
when the rules are empty.
2014-10-02 19:42:48 -07:00
23238aa7ac
Handle functions in $root scope.
2014-10-02 15:04:14 -07:00
2397aa1587
Merge pull request #45 from orsonmmz/subprogram
...
Subprograms
2014-10-02 14:14:52 -07:00
b4119de9b1
Merge branch 'master' of github.com:steveicarus/iverilog
2014-10-02 14:10:10 -07:00
338a0eb11a
Get $root scope tasks/fuctions down to the ivl_target API.
2014-10-02 14:09:27 -07:00
fde6525acb
vhdlpp: Libraries are searched for subprograms during the ExpFunc elaboration.
2014-10-01 14:56:32 +02:00
c5fee8bdb9
Elaborate root tasks/functions.
2014-09-30 16:06:32 -07:00
194a950f8d
vhdlpp: Elaboration of ExpFunc parameters fallbacks to the types given in the Subprogram header.
2014-09-30 15:59:46 +02:00
9951521212
vhdlpp: Subprogram parameters are taken into account when distinguishing between function calls and vector elements.
2014-09-30 15:59:46 +02:00
9e856810b9
vhdlpp: Workaround to avoid translation of variables to wires in functions.
2014-09-30 15:59:45 +02:00
675b7d8efa
vhdlpp: Support for std_logic_vector return type in functions.
...
VHDL does not allow to specify the size of returned std_logic_vector,
whereas Verilog requires the size to be known in advance. The size of
the vector is determined by checking the type of expression used in the
return statement.
2014-09-30 15:58:26 +02:00
e352bea476
vhdlpp: Support for variable declarations in subprograms.
...
Fixes sorrymsg: "variable_declaration not supported."
2014-09-30 15:58:13 +02:00
747e656a0e
vhdlpp: Added ScopeBase::transfer_from() method.
2014-09-30 15:00:55 +02:00
7b5470c8a7
vhdlpp: Subprogram class inherits from ScopeBase.
2014-09-30 15:00:55 +02:00
985a3eb206
Update lz4 files to the latest from GTKWave
2014-09-26 15:04:55 -07:00
e1ec27e18c
Merge pull request #43 from orsonmmz/record_elab
...
Elaboration & emit functions for aggregate expressions used as record initializers.
2014-09-18 12:59:28 -07:00
d13e488f4c
Merge pull request #42 from orsonmmz/const_package
...
Enable constant initializers that require elaboration in packages.
2014-09-18 12:58:19 -07:00
f5dd2ac87e
vhdlpp: Aggregate expressions for records can be specified in any order.
2014-09-17 16:32:56 +02:00
Cary R
Martin Whitaker
Stephen Williams
Maciej Suminski