69a96112e8
Fix null-pointer when trying to dump null statements.
2016-10-27 10:55:50 -07:00
f827e4f748
Pop current_block_stack after for_variable_declaration and foreach.
2016-10-27 10:29:18 -07:00
991d7d7582
Fix indentation in previous patch.
2016-10-20 16:25:34 +01:00
1f9bf656ed
Adding implementation of NetEvWait::nex_input to handle event controls inside always@(*) blocks
2016-10-20 16:19:55 +01:00
a9f1f306f1
Replace strndup with strdup and fix a few potential buffer overrun bugs.
...
strndup is not available in Windows.
2016-10-14 22:19:33 +01:00
edb922f613
Use correct format strings for PLI_UINT64 in printf/scanf functions.
2016-10-14 20:35:36 +01:00
7ddc514518
Allow library files to be specified on the iverilog command line.
...
This was already supported in command files, using the '-v' flag.
'-v' is already in use on the command line, so use '-l' instead,
and make that an alias for '-v' in command files.
2016-10-02 18:57:32 +01:00
0fdf29e099
Fix for GitHub issue #117 - delays in VPI simulation time callbacks.
...
Change cbReadWriteSynch and cbReadOnlySynch to interpret the passed
time value as a relative delay, not an absolute time. This matches
the behaviour of other simulators.
2016-09-25 20:43:58 +01:00
e56e52bc42
Merge branch 'master' of github.com:steveicarus/iverilog
2016-09-19 12:59:41 -07:00
f32b64f497
Fixed warnings about shifting a negative value
2016-09-19 12:54:15 -07:00
151f061298
vhdlpp: Removed unused parameters to mute warnings
2016-09-19 12:53:41 -07:00
3710d35dd1
Added missing brackets
2016-09-19 12:53:06 -07:00
aaf0a9e623
vhdlpp: Accept uppercase letters in based literals
2016-09-19 12:46:24 -07:00
080dd0323d
Fix for GitHub issue #127 - coerce output ports to inout when necessary.
2016-09-17 19:20:48 +01:00
5853e32f82
Fix some cppcheck warning issues
2016-09-13 23:45:25 -07:00
c706c5dd90
The array properties can be available in a constant context
...
For most arrays the various properties are available as constant
values and can be evaluated in the compiler.
2016-09-11 14:25:00 -07:00
3c9b39846c
Use gn_system_verilog() where appropriate.
...
Replace explicit comparisons against generation_flag with calls to
the gn_system_verilog helper function, both for code clarity and
to fix a couple of bugs. Also simplify the implementation of the
function, as we already rely on the generation_flag enumeration
being an ordered list.
2016-09-08 23:00:48 +01:00
fb2cd4775f
Added missing compilation instruction on README
2016-09-04 00:51:57 -03:00
301e85a8ca
Merge pull request #122 from orsonmmz/resize_fix
...
vhdlpp update
2016-09-02 10:01:02 -07:00
5dd2e6a7c8
vhdlpp: Corrected standard library function headers
2016-09-01 12:08:44 +02:00
8ba3d62071
vhdlpp: Better resize() implementation.
...
Previous version did not work well with signed expressions or expressions that
were temporarily resized (e.g. a + 32'd42, where a is a[7:0]).
2016-09-01 12:08:44 +02:00
bab39dae19
vhdlpp: Some of the standard library functions are imported only on request
...
Previously they have been always enabled, now it is required to put a
'use' directive.
2016-09-01 12:08:44 +02:00
089dd037d6
vhdlpp: Use the wider variable size for arith operations on (un)signed
2016-09-01 12:08:44 +02:00
25f4a54852
vhdlpp: Subprograms are matched once. ExpFunc::probe_type() return exact type
2016-09-01 12:08:44 +02:00
8f86004100
vhdlpp: Clearer error messages
2016-09-01 12:08:44 +02:00
07543315cf
vhdlpp: Stricter array type matching
...
Arrays type match if they have a common parent, instead of the
element type. Now (un)signed & std_logic_vector types do not match,
as it should be in VHDL.
2016-09-01 12:08:43 +02:00
fe77b0ac87
vhdlpp: VTypeArray::dimensions() returns std::vector<range_t>
2016-09-01 12:08:43 +02:00
643a3f2f2c
vhdlpp: Do not evaluate generics.
...
They might change depending on the instance, so they cannot be evaluated using the default value.
2016-09-01 12:08:43 +02:00
ed3e67926f
vhdlpp: Evaluate conditional signal assignments upon simulation start.
2016-09-01 12:08:43 +02:00
798adc9863
vhdlpp: Support for unary sign operator.
2016-09-01 12:08:43 +02:00
9e95ae5859
vhdlpp: Moved Exp*::dump() methods from debug.cc to expression_debug.cc.
2016-09-01 12:08:39 +02:00
d44c814bab
Remove .alias records from vvp generated code.
...
Net arrays can be handled by nets directly, instead of creating
.alias records.
2016-08-31 14:05:09 -07:00
41075a45e6
Fix for GitHub issue #121 - correctly determine ivl_root.
...
Pull request #116 added the ability for the iverilog driver to determine
ivl_root from the location of the iverilog executable (this is needed to
support relocation at the time iverilog is installed). However, the code
did not support the possible variations in the library path name.
2016-08-24 00:00:24 +01:00
a2fbdeff78
Add some pass by reference to vvp
2016-08-14 22:26:16 -07:00
ad5a7f7ca3
Update cppcheck vvp suppression file
2016-08-14 21:18:55 -07:00
d0e0776910
Make the base class match the derived classes regarding passing by reference
2016-08-14 21:18:44 -07:00
255701a787
Fix space issue
2016-08-14 20:55:55 -07:00
5f1e63604c
Update cppcheck vpi suppression file
2016-08-14 20:53:57 -07:00
9cf23b4c3b
Make getting ivl_root more robust
2016-08-14 19:41:35 -07:00
446e825ed3
Fix space issues
2016-08-14 19:37:40 -07:00
1d4230472a
Fix getting timeunit outside of module to use a defined check value
2016-08-14 17:26:23 -07:00
13189f7431
Update fstapi.c to latest from GTKWave
2016-08-14 12:46:48 -07:00
b51e58fa9d
Fix for br1007 - out-of-range constant bit select should be a warning.
...
An out-of-range constant bit select on the LHS of an assignment was being
treated as an error, whereas an out-of range constant part select would
only result in a warning. In any other context, either case would result
in a warning, so convert the error to a warning.
In addition, all warnings for out-of-range or undefined constant bit/part
selects should be controlled by -Wselect-range.
2016-08-08 22:10:16 +01:00
8461e1d9c4
Fix vlog95 target to handle hierarchical references in root-level tasks.
2016-07-26 22:01:22 +01:00
2bc42fc6e2
Fix for GitHub issue #104 - assigning hierarchical signal from top level task.
...
When emitting a design, all scopes must be emitted before emitting any
top level task/function/method definitions, otherwise hierarchical
references can't always be resolved.
2016-07-26 22:01:22 +01:00
7d5f6c551a
Fix unused variable warning and assumed buffer size from last merge.
2016-07-23 12:01:58 +01:00
191811f78f
Merge branch 'conda-fix' of https://github.com/tfors/iverilog
2016-07-23 11:40:09 +01:00
b1b91f49c8
Update vlog95 target to handle timescales for root scope tasks/functions.
2016-07-23 00:10:01 +01:00
27213f2af8
Fix for GitHub issue #115 - synthesis aborts on case with max guard of 0.
...
The calculation of the required multiplexer width was incorrect for
the corner case of a single guard value of zero.
2016-07-22 23:09:36 +01:00
7bed181f68
Support timescales in design units that aren't inside a module.
...
SystemVerilog allows tasks, functions, and classes to be defined at the
root level or inside packages, so we can't rely on an enclosing module
being present to provide the timescale.
2016-07-22 22:48:20 +01:00
Henry Wong
Martin Whitaker
Stephen Williams
Maciej Suminski
Cary R
Daniel Andrade