Commit Graph

4117 Commits

Author SHA1 Message Date
Cary R 4d8db7b5bc Clean pulse events for real signals.
This patch cleans pulse events for real signals. Not doing this
can produce invalid results under some conditions.
2008-02-13 15:43:19 -08:00
Cary R 2bab415626 Add message for unsupported release of part/bit select.
This patch adds a real error message instead of an assert when
someone attempts to release a part or bit select. I plan to work
on the real functionality soon.
2008-02-13 15:37:53 -08:00
Stephen Williams 110bc2e6eb Merge branch 'master' of ssh://steve-icarus@icarus.com/home/u/icarus/steve/git/verilog 2008-02-13 15:27:39 -08:00
Cary R 331faa2217 Add signed bit based power to continuous assignments.
This patch adds the power operator for signed bit based values
in a continuous assignment. It also fixes a few other power
expression width problems. The expression width is still not
calculated correctly, since the correct method can produce huge
possible bit widths. The result is currently limited to the width
of the native long. This is because lround() is used to convert
from a double to an integer. A check in the code generator protects
the runtime from this limitation.
2008-02-11 20:06:41 -08:00
Stephen Williams f2ff25bfef Dump delays of constants. 2008-02-09 22:20:01 -08:00
Stephen Williams bc1d3eb7cd Add support for generate case
Generate case is a complex generate scheme where the items are
sub-schemes of the case generate itself. The parser handles them
something like nested generate statements, but storing the case
guards as the test expression. Then the elaborator notes the
case scheme and reaches into the case item schemes inside to make
up tests, select the generate item, and elaborate.
2008-02-09 22:19:42 -08:00
Larry Doolittle 63e2aa8d1a refine man page treatment of -d
also renames config file option from scope to scopes,
for consistency with the source code, and adds a
wiki reference to the man page.
2008-02-08 15:30:21 -08:00
Stephen Williams 0ac36dc5af Merge branch 'master' of steve-icarus@icarus.com:git/verilog 2008-02-06 18:38:55 -08:00
Stephen Williams 3a300725de Output delays for part select nets.
Implement net delays for part select devices.
2008-02-06 18:37:42 -08:00
Cary R 85229a6cdc Add unsigned bit based power to continuous assignments.
This patch adds the power operator for unsigned bit based values
in a continuous assignment. It also refactors the power code for
normal expressions and continuous assignments.
2008-02-06 14:38:16 -08:00
Cary R 47d1d981d5 Mangle the scope for user functions in a continuous assignment.
User functions called in a continuous assignment were not getting
their scope mangled. This is needed to handle arrayed instances and
possibly other things.
2008-02-06 14:28:08 -08:00
Stephen Williams fb63bf7dba Compile portability issues. 2008-02-05 20:36:57 -08:00
Martin Whitaker 3d2e791e52 Fix for pr1887168.
This patch fixes some bugs in the implementation of signed integer
division with wide operands in constant expressions and adds support
for signed integer modulus with wide operands in constant expressions.
It also removes a few redundant lines of code.
2008-02-05 15:48:07 -08:00
Larry Doolittle aaf8908676 Document new -d flag to driver
followup to commit 6256dd8040
2008-02-05 15:44:14 -08:00
Cary R 4cf8920e48 Fix trimming of unsigned verinum values.
Incorrect trimming of unsigned verinum values was causing the
compilers unsigned constant verinum pow function to give
incorrect results. This patch restores the pow compile time
optimization and fixes the trimming to always leave a single
zero in the MSB.
2008-02-05 15:40:21 -08:00
Cary R e82293c981 Add unsigned bit based power support to normal expressions.
This patch adds bit based power support to normal expressions.
It also pushes the constant unsigned bit based calculation to
the runtime until the bit based method can be copied to the
compiler. Continuous assignments also need to use this type
of calculation.
2008-02-05 15:33:51 -08:00
Stephen Williams 1b410f0c7d Factor code for processing parameters and localparams
Replace some redundant code with a single function that handles the
elaboration and type management of parameters identically.
2008-02-05 13:37:33 -08:00
Martin Whitaker 51b1804660 Fix for pr1885847.
Currently, if a localparam declaration does not include a type or
range, the RHS expression is cast to an unsigned value. This patch
changes this to make the localparam inherit the type of the RHS
expression, as is done for parameter declarations and is specified
by the Verilog-2001 standard.
2008-02-05 13:06:42 -08:00
Cary R 40064b3181 Catch that we do not currently support unsigned bit based power.
This patch adds a check and prints a warning message when the power
operator is used with unsigned bit based values. It also fixes a couple
of typos and adds an asserts if the above power operator happens to
get to the tgt-vvp back end.
2008-02-04 13:35:44 -08:00
Larry Doolittle 0e6d6b7416 Fix typos in vpi/sys_display.c
Fallout from me trying to understand the origin of pr1780480
and pr1830834.  Too bad I don't understand c++ and vvp as
well as I understand English!

(Spelling and grammer fixes in comments. -ed.)
2008-02-04 13:33:24 -08:00
Larry Doolittle f4cf7b1799 Cleanup from yesterday's "Add more error checking" patch
Removes const char related compiler warnings,
tidies up mainline code by abstracting the human_readable_op() routine
2008-02-04 13:30:30 -08:00
Michael Witten 9c0d2c13c9 [PATCH] Removed #include asm/page.h on GNU/Linux
vvp/main.cc was including asm/page.h on GNU/Linux
systems, though that file does not often exist and
is not necessary.

Signed-off-by: Michael Witten <mfwitten@mit.edu>
2008-02-04 13:22:32 -08:00
Stephen Williams f1f2806e3c Get delays of signed extended continuous assignments right.
Padding and continuous assignment caused problems if the continuous
assignment includes a delay. The problem is that the padding was
not necessarily included in the delay. Rework the elaboration to
make sure the padding is indeed included in the delay.
2008-02-01 20:13:23 -08:00
Cary R db851c235f Add more error checking for operators that cannot use real values.
This patch adds some checks to verify that  shifts, the reduction
operators and the bit wise operators are not used with real values.
It also includes a few other cleanups.
2008-01-31 20:15:04 -08:00
Cary R 1595ae79fd Add support for real power (**) in normal expressions.
This patch adds support for the real power (**) operator in
normal expressions.
2008-01-31 19:54:37 -08:00
Cary R f049426f25 Add support for real % in a continuous assignment.
This patch adds conditional support (2001X) for the real modulus
operator in a continuous assignment.
2008-01-31 16:56:11 -08:00
Cary R 5e8a1bd8cc Add power operator (**) for real values in a continuous assignment.
This patch adds the power operator for real values in a continuous
assignment.
2008-01-31 16:48:52 -08:00
Cary R fa759c1802 Fix problem with delay at t0 when only some of the bits change.
This patch makes sure the delay is calculated correctly when only some
of the bits change and you are comparing against the initial (t0) value.
Basically you have to check the initial value against all the bits in
the new signal not just the first bit since the order that bits change
is not deterministic.
2008-01-31 16:42:51 -08:00
Cary R 4c5481f254 Add delays for shifts, concatenation and replication in a CA.
This patch add delays in continuous assignments for the shift operators,
concatenations and replications. It also reports an error if the user
attempts to take the modulus of a real value.

This patch uncovers a couple other problems in the system. I am trying
to fix one of them. I will report the other problem shortly.
2008-01-31 16:39:12 -08:00
Cary R 1609de6ed9 Fix some bit based delays in continuous assignments.
This patch fixes some of the delays in bit based continuous
assignments (unary -, unary +constants, string constants,
reduction operators and user functions).

Use draw_lpm_output_delay() in all functions that need it.
2008-01-29 20:27:53 -08:00
Larry Doolittle d9ac146b8f Spelling fixes
only comments and documentation
some punctuation and capitalization for good measure
Changelogs are purposefully untouched
2008-01-29 20:24:24 -08:00
Larry Doolittle 31afec57b1 Fix for pr1879226, large constant shift values
Addresses pr1879226 on a couple of levels.  Analysis:

NetNet* PEBinary::elaborate_net_shift_() didn't flag dist==lwidth
as a case where all bits of the input are shifted away, which made
it create a real concatenator for this case.  It attempted to create
NetNet*tmp with zero width, which doesn't work; (lsb,msb) ends up
as (0,-1), which is later interpreted as a 2-bit wide net.

Added an assert to the NetNet constructor to catch any other lurking
attempts to create zero-width nets.

Added short-circuit code to handle the case where all bits of the input
are shifted away.  This case used to be "handled" by an assert failure.
2008-01-29 09:31:16 -08:00
Stephen Williams 76039cf595 Merge branch 'master' of steve-icarus@icarus.com:git/verilog 2008-01-28 21:33:14 -08:00
Stephen Williams 685095b229 Support delay of user function output
When used in continuous assignments, user defined functions may have
delayed output. Handle that by generating the proper .delay node when
needed to delay the output of a .ufunc node.
2008-01-28 21:29:03 -08:00
Stephen Williams abfccb65e9 User defined functions take real arguments
Allow user defined functions to take real value arguments and return
real value results in net contexts. Use the data type of the nets
attached to the ports to define the data types of the arguments and
return value.
2008-01-28 18:57:55 -08:00
Larry Doolittle 388bb93beb Spelling fixes
only comments and documentation
2008-01-28 09:15:39 -08:00
Stephen Williams 1eb581ab37 Merge branch 'master' of ssh://steve-icarus@icarus.com/home/u/icarus/steve/git/verilog 2008-01-28 09:13:33 -08:00
Stephen Williams 2f9ad47890 Merge branch 'master' of steve-icarus@icarus.com:git/verilog 2008-01-27 18:25:11 -08:00
Larry Doolittle 47d65034db Spelling fixes
mostly comments, but includes some identifiers and message text
2008-01-27 18:18:13 -08:00
Stephen Williams b297a0a9fe Remove support for vvp32 build
Remove configure and Makefile support for the vvp32 build. Remove
also the libdir64 support.
2008-01-25 17:33:32 -08:00
Larry Doolittle 6256dd8040 Add support for ivl debug flags. 2008-01-25 11:16:44 -08:00
Stephen Williams 5ec91ec914 Add datarootdir to makefiles
It seems that later versions of autoconf expect datarootdir to be
use and set.
2008-01-24 12:10:31 -08:00
Stephen Williams 76164d7711 Rework compile-time evaluation of LT and GT
There was much redundant code in the compile-tile handling of the
less-then and greater-then of constant expressions, and much of it
was buggy. Unify much of the code and squeeze out the bugs so that
compile-time evaluations come out correctly.
2008-01-23 20:43:13 -08:00
Stephen Williams 89bf16b21e Signed-ness of parameters
Propagate the signedness of named parameters when they are evaluated.
2008-01-22 20:16:43 -08:00
Stephen Williams 5b17f2039a Fix bug in eval of <= compare
The compiler attempts to precalculate the results of <= comparisons.
Fix a few corner cases where the arguments are signed. Also fix the
important test of constant against non-constant where we try to test
if the non-constant value can possibly make the test fail.
2008-01-21 22:05:50 -08:00
Stephen Williams db25bba0d0 Fix assertion fail handling certain conditional delays
When conditional delays are in use, it is sometimes possible for there
to be no delays available for a given input event. In that case, skip
the delay processing for that case instead of crashing.
2008-01-21 19:57:17 -08:00
Cary R 10d25d2b88 Support delays for all operators in a continuous assignments.
Previously only the logical operators (~, &, |, ^, etc.) supported a
delayed value in a continuous assignment. This patch should extend this
to all operators. An extensive check of real values was done. The same
will be done shortly for bit based nets.

Checks for constructs currently unsupported in continuous assignments
provide a more explicit message (** operator, real user functions,
{!, && and ||} operators with a real argument).
2008-01-21 18:21:31 -08:00
Stephen Williams 3ea72109f8 Read and include sign of scanned decimal.
Fix simple bug where negative values read from the source file were
not getting their sign. The fix was proposed in pr1876738.
2008-01-21 18:11:28 -08:00
Stephen Williams b6b7d704b2 Clean up lexing of net literals.
The matching of net literals (i.e. Cx<> and T<> symbols) should not get
in the way of properly matching other symbols.
2008-01-21 17:52:40 -08:00
Stephen Williams 32d3e5ac46 Better formatting of Cr<> label for real valued drivers.
Rework the encoding of a real value in the Cr<> label to be similar to
the format used by the %loadi/wr instruction. This mantissa-expoment
format better carries all the bits of the desired real value with
plenty of fidelity and range.
2008-01-19 16:27:09 -08:00