Commit Graph

73 Commits

Author SHA1 Message Date
Maciej Suminski c6f934964f vhdlpp: NOT is translated to either ~(...) or !(...) depending on the argument type. 2015-06-24 23:53:32 +02:00
Maciej Suminski b666b9c0bf vhdlpp: Fixed a few memory leaks. 2015-06-24 23:53:32 +02:00
Maciej Suminski 169228ad0f vhdlpp: Refactored the way of handling standard VHDL library functions. 2015-06-24 23:53:31 +02:00
Maciej Suminski 5a0d967682 vhdlpp: More renaming in ExpConditional. 2015-06-24 23:53:31 +02:00
Maciej Suminski 49efe6573c vhdlpp: Minor ExpConditional refactoring.
Merged cond_ and true_clause_ to else_clause_ list to make
code more generic.
2015-06-24 23:53:31 +02:00
Maciej Suminski ea12c0fe23 vhdlp: Renamed ExpConditional::else_t to ExpConditional::option_t. 2015-06-24 23:53:31 +02:00
Maciej Suminski d6ff1946f9 vhdlpp: Support for time expressions. 2015-06-08 18:42:52 +02:00
Larry Doolittle c8fe897446 vhdlpp: and_reduce() and or_reduce() functions. 2015-04-24 13:46:30 +02:00
Maciej Suminski a5138e238f vhdlpp: Added missing std_logic values in ExpChar and ExpString::emit(). 2015-04-23 11:57:27 +02:00
Maciej Suminski d5ffb55bfd Corrected ambiguous copyright info. 2015-03-27 18:57:40 +01:00
Maciej Suminski afaedbd06d vhdlpp: Corrected to_integer() & resize() functions.
to_integer() handles sign and resize() really applies size casting.
2015-03-27 14:53:43 +01:00
Maciej Suminski d1dc98b7f7 vhdlpp: Changed the workaround for accessing localparam arrays & records. 2015-03-07 20:47:20 +01:00
Maciej Suminski 1de3fb1625 vhdlpp: "resize" function. 2015-03-06 17:58:04 +01:00
Maciej Suminski e33b8b4dde vhdlpp: VType::get_width() uses information from Scope to determine the type width. 2015-03-06 17:58:04 +01:00
Maciej Suminski 9128eb67b9 vhdlpp: Evaluates attributes if possible. 2015-03-06 17:32:25 +01:00
Maciej Suminski afbda099fb vhdlpp: Workaround to handle constant arrays of vectors & records. 2015-03-06 17:32:25 +01:00
Maciej Suminski a42b056b24 vhdlpp: Alternative way of accessing constant arrays of vectors. 2015-03-06 17:32:25 +01:00
Maciej Suminski 5884879b02 vhdlpp: to_integer() function. 2015-02-19 17:07:41 +01:00
Maciej Suminski 763c6fe3c9 vhdlpp: Support for shift operators (SRL, SRR, SRA, SLA).
To be done: ROR & ROL.
2015-02-17 10:15:57 +01:00
Maciej Suminski cdf18de10e vhdlpp: Make integer expressions sized during the emission step. 2015-02-05 16:20:49 +01:00
Maciej Suminski 51ce9f1a60 vhdlpp: Minor correction for casting to integer. 2015-02-05 11:25:03 +01:00
Maciej Suminski 25c3798248 vhdlpp: Elaborate and emit functions work with ScopeBase instead of Architecture. 2015-02-04 16:57:43 +01:00
Maciej Suminski d4dd635bf6 vhdlpp: Added ExpNew class. 2015-02-04 16:57:43 +01:00
Maciej Suminski 9b3bd039bb vhdlpp: Added ExpCast class. 2015-02-04 16:57:42 +01:00
Maciej Suminski c55a013162 vhdlpp: Support for integer() function.
Note: I could not find any info about the integer() function, but it is
used in the VHDL standard packages (e.g. math_real, see:
http://www.csee.umbc.edu/portal/help/VHDL/packages/mathpack.vhd)
Real numbers are rounded, this is compatible with ModelSim behavior.
2014-10-17 14:53:59 +02:00
Maciej Suminski 97df6183a9 vhdlpp: Emit '-' std_logic value as 'x'.
Note: It is not a direct ("don't care" vs "unknown"), but I could not
find anything that suits better.
2014-10-17 14:13:06 +02:00
Maciej Suminski 76aab15798 vhdlpp: Minor code cleaning. 2014-10-15 10:51:21 +02:00
Maciej Suminski 1333bc54a2 vhdlpp: Support for 'left & 'right attributes. 2014-10-08 10:05:04 +02:00
Maciej Suminski 7b5470c8a7 vhdlpp: Subprogram class inherits from ScopeBase. 2014-09-30 15:00:55 +02:00
Maciej Suminski 94abef195a vhdlpp: Commented out named assignment for records. 2014-09-17 16:30:44 +02:00
Maciej Suminski 54696e0127 vhdlpp: Elaboration & emit support for aggregate initializer expressions in records. 2014-09-17 11:24:16 +02:00
Maciej Suminski cb03802a17 vhdlpp: Added VTypeArray::basic_type() to cope with
arrays based on typedefs.
2014-09-15 12:10:05 +02:00
Maciej Suminski 10446df80e vhdlpp: Invert range in ExpAggregate when necessary. 2014-08-22 16:23:22 +02:00
Maciej Suminski 0a2100c87f vhdlpp: Turn on the reg_flag for types that cannot be packed. 2014-08-22 16:22:59 +02:00
Maciej Suminski 5ed60a151f Added support for real type in vhdlpp. 2014-08-06 15:00:35 +02:00
Larry Doolittle be17bfc0e9 Spelling fixes
Mostly comments.
One user-visible string ("Evalutated to ") changed in the debug_eval_tree case.
2014-01-30 15:34:20 -08:00
Stephen Williams d630e4dfe9 Elaborate VHDL entity port types/expressions.
We need to elaborate expressions so that function calls in
expressions (i.e. ranges) get bound to their proper scope.
This binding is in turn used to emit package scopes. This
is particularly interesting for ports of entities.
2013-06-12 14:21:35 -07:00
Stephen Williams 0fcd2d9db6 Handle rising_edge and falling_edge functions. 2013-06-12 14:21:35 -07:00
Stephen Williams bc77a19059 Use $ivl_unsigned to implement VHDL to_unsigned function.
The VHDL to_unsigned function with to arguments is best handled
in the ivl elaborator, so have it generate an $ivlh_to_unsigned
function call in the vhdlpp code, and implement it in the ivl
core.

Also, implement the 'length attribute as a $bits() call for
similar reasons.
2013-06-12 14:09:08 -07:00
Stephen Williams 6394a4d78d Rework scope types and constants so we can tell imported from local names.
The package emit of types and constants needs to know which names are
from the current type and which are imported from libraries. Rework
the scope handling of those names so that the information is preserved.
2013-06-12 14:09:07 -07:00
Stephen Williams c14134aa2e Handle genvar variables in expressions.
In generate for blocks, there is a genvar that can be used in
expressions within the generate block. Generate this genvar in
the generated output, matched to the generate scope.
2012-09-07 15:14:48 -07:00
Stephen Williams 85e000ed0c Handle prefix expressions that include array index expressions. 2012-09-03 16:00:10 -07:00
Arun Persaud f5aafc32f9 updated FSF-address 2012-08-29 10:12:10 -07:00
Cary R 4313fbbf1f Fix space errors in various files 2012-08-16 11:13:32 -07:00
Stephen Williams 621c09105c Sort the typedef emits so that types are emitted in the order used.
It is common for typedefs of complex types to use further typedefs.
Emit the type definitions depth first so that the types that are used
are defined first. This reduces the need for pre-declaration of types.
2012-05-22 17:31:27 -07:00
Stephen Williams 63b7fe059d Reword concat to handle aggregate arguments.
When concatenation expressions have aggregate arguments, we need to
get the type of the result down to the aggregate expressions so that
it can know how to interpret the elements.
2012-05-22 17:31:26 -07:00
Stephen Williams 71d2401221 Handle VHDL records.
Elaborate records and emit them as packed SV records. Also handle
record members so handle name prefixes.

While we are at it, handle some cases of array aggregate expressions.
2012-05-22 17:31:26 -07:00
Stephen Williams 7eb89c5548 Parse name prefix syntax for record member reference.
When signals/variables are records, they are often referenced by
their members, using a prefix.name syntax. Parse that syntax and
generate "sorry" messages in elaboration.
2012-05-22 17:31:25 -07:00
Stephen Williams 9b816f6478 Add support for nested when/else expressions. 2012-05-22 17:31:25 -07:00
Cary R bcb963a235 Fix Cygwin compile problem (replace abs() call with ?:
This patch fixes a compile problem in Cygwin where there are two
definitions for abs() that do not match so the C++ code doesn't know
which one to call. To avoid the whole mess replace the call to abs()
with the appropriate ?: construct.
2011-11-17 14:30:33 -08:00